Adaptive peripheral component interconnect express link substate initiation for optimal performance and power savings

An apparatus comprising:

• a Peripheral Component Interconnect Express (PCIe) interface adapted to couple the apparatus to a PCIe link;
• and
• a controller configured to determine that a first burst of data is being transmitted on the PCIe link, wherein the data in the first burst of data is encapsulated in a plurality of packets configured in accordance with a PCIe bus protocol, and wherein during transmission of the first burst of data the controller is further configured to:
• determine when the PCIe link has entered an idle state;
• enable a timer adapted to signal when an entry latency period has elapsed after determining that the PCIe link has entered the idle state after completing transmission of a first packet in the plurality of packets;
• cause one or more circuits of the PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, wherein the PCIe link becomes active when a second packet in the plurality of packets is available for transmission;
• increase the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data exceeds a first threshold that defines a maximum number of entries into the low-power state per burst of data;
• and
• update the first threshold based on performance of the PCIe link, including the number of entries of the PCIe interface to the low-power state counted during transmission of the first burst, thereby obtaining an updated first threshold to be used in a subsequent second burst.

An apparatus comprising:

• means for determining activity on a PCIe link, including determining when a first burst of data is being transmitted on the PCIe link, wherein the data in the first burst of data is encapsulated in a plurality of packets configured in accordance with a PCIe bus protocol;
• means for managing power consumption in a Peripheral Component Interconnect Express (PCIe) interface, and configured to transition the PCIe interface between at least a first state and a second state;
• means for configuring a timer, wherein the means for configuring the timer is adapted to signal when an entry latency period has elapsed after the means for determining activity on the PCIe link has determined that the PCIe link has entered an idle state between transmissions of a first pair of packets in the first burst of data transmitted on the PCIe link;
• and
• means for modifying the entry latency period based on a number of entries of the PCIe interface to a low-power state that occurs during transmission of the first burst of data, wherein the means for modifying the entry latency period is configured to:
• increase the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data exceeds a first threshold that defines a maximum number of entries into the low-power state per burst of data;
• and
• update the first threshold based on performance of the PCIe link, including the number of entries of the PCIe interface to the low-power state counted during transmission of the first burst, thereby obtaining an updated first threshold to be used in a subsequent second burst,
• wherein the means for managing power consumption is configured to cause one or more circuits of the PCIe interface to enter the low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active.

A non-transitory processor-readable storage medium comprising code for:

• determining that a first burst of data is being transmitted on a Peripheral Component Interconnect Express (PCIe) link, wherein the data in the first burst of data is encapsulated in a plurality of packets configured in accordance with a PCIe bus protocol;
• configuring a timer to signal when an entry latency period has elapsed after determining that the PCIe link has entered an idle state after completing transmission of a first packet in the plurality of packets;
• causing one or more circuits of a PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, wherein the PCIe link becomes active when a second packet in the plurality of packets is available for transmission;
• increasing the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the first burst of data exceeds a first threshold that defines a maximum number of entries into the low-power state per burst of data;
• and
• updating the first threshold based on performance of the PCIe link, including the number of entries of the PCIe interface to the low-power state counted during transmission of the first burst, thereby obtaining an updated first threshold to be used in a subsequent second burst.