Systems and methods for controlling instantaneous current changes in parallel processors

A system for controlling an instantaneous current change in a parallel processor, the system comprising:

• an array of computing elements of the processor, the computing elements configured to operate independently of each other in parallel;
• a controller configured to determine a transition from a first activity level of the array to a second activity level of the array;
• and
• the controller configured to control the array to minimize the instantaneous current change from the transition from the first activity level to the second activity level;
• the controller further comprises a clock rate controller configured to control the frequency of a core clock of the processor;
• the clock rate controller is further configured to first decrease the frequency of the core clock and then incrementally increase the frequency of the core clock, wherein the first activity level is an idle state and the second activity level is an active state.

A system for controlling an instantaneous current change in a parallel processor, the system comprising:

• an array of computing elements of the processor, the computing elements configured to operate independently of each other in parallel;
• a local memory coupled to the array of computing elements, the local memory configured to buffer a stream of operands provided to the array of computing elements;
• the local memory is configured to receive a plurality of operands in an order different from an order in which the local memory provides the plurality of operands to the array of computing elements;
• and
• a controller configured to determine, based on movement of the operands through the local memory, a transition from a first activity level of the array to a second activity level of the array;
• the controller is configured to control the array to minimize the instantaneous current change from the transition from the first activity level to the second activity level, the controller further comprises:
• an activity monitor which detects the first activity and second activity levels of the array, and a clock rate controller;
• the clock rate controller configured to control the frequency of a core clock of the processor.