Area-efficient scalable memory read-data multiplexing and latching

An apparatus comprising:

• a driver circuitry having a sense amplifier and an output coupled to a shared-read-data signal path, the driver circuitry to either drive its output to a value of a sensed memory bit during a read operation of its sense amplifier, or not drive its output during a standby mode of its sense amplifier;
• a receiver-and-keeper circuitry having cross-coupled clocked inverters, one of the clocked inverters having an input coupled to the shared-read-data signal path and an output coupled to an inverse-data signal path;
• and
• an inverter having an input coupled to the inverse-data signal data path and an output coupled to a data signal path.

A system comprising a memory, a processor coupled to the memory, and a wireless interface for allowing the processor to communicate with another device, the processor including:

• a first circuitry having an output coupled to a shared-read-data signal path, the first circuitry to either drive its output to a value based on a sensed memory bit, or not drive its output;
• a second circuitry having a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path;
• and
• a third circuitry having an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.