Low noise bandgap reference apparatus
AssigneeIntel Corporation
InventorMatthias Eberlein
Life of this patent
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Abstract
An apparatus is provided which includes: a first supply node; a second supply node; a first transistor coupled to the first supply node, the first transistor is to provide a first current which is complementary to absolute temperature (CTAT); a second transistor coupled to the first supply node, the second transistor is to provide a second current which is proportional to absolute temperature (PTAT); a resistive device coupled in series at a node with the first and second transistors, and coupled to the second supply node, wherein the node is to sum the CTAT and the PTAT currents.
Claims30
An apparatus comprising:
- a first supply node;
- a second supply node;
- a first transistor coupled to the first supply node, wherein the first transistor is to provide a first current which is complementary to absolute temperature (CTAT);
- a second transistor coupled to the first supply node, wherein the second transistor is to provide a second current which is proportional to absolute temperature (PTAT);
- a resistive device coupled in series at a node with the first and second transistors, and coupled to the second supply node, wherein the node is to sum the CTAT and the PTAT currents;
- and
- a current mirror coupled to the first supply node and connected to the first and second transistors such that respective gate terminals of the first and second transistors are connected to separate nodes of the current mirror, wherein the separate nodes are connected to a same transistor of the current mirror.
An apparatus comprising:
- a current mirror coupled to a first power supply node;
- a pair of bi-polar junction devices coupled to the current mirror;
- a first transistor connected to the first power supply node, the current mirror, and the pair of bi-polar junction devices such that the first transistor is to be biased by a feedback electrical path comprising the current mirror and the pair of bi-polar junction devices;
- a second transistor coupled to the first supply node and is to be biased by the feedback electrical path;
- and
- a resistor coupled in series with the first transistor, and to a second supply node wherein the first supply node is a power supply node which provides a power supply less than 1 V, and wherein the second supply node is a ground.
An apparatus comprising:
- a first circuitry to provide a first current which is complementary to absolute temperature (CTAT);
- a second circuitry to provide a second current which is proportional to absolute temperature (PTAT);
- and
- a node to sum the first and second currents and to provide a bandgap reference voltage which is to be less than 1 V, wherein the first and second circuitries comprises first and second transistors, respectively, which are connected to a current mirror such that respective gate terminals of the first and second transistors are connected to different nodes of the current mirror, and wherein the different nodes are connected to a same transistor of the current mirror.
A reference generator apparatus, comprising:
- a current mirror comprising a first p-type device and a second p-type device;
- a first bi-polar junction transistor (BJT) connected to the first p-type device;
- a first resistive device coupled in series with the second p-type device;
- a second BJT coupled to the second p-type device such that the first resistive device is connected in series with the second BJT;
- a third p-type device having a gate terminal connected to the second p-type device;
- a second resistive device coupled to the third p-type device;
- a fourth p-type device connected to the third p-type device;
- a third resistive device coupled to the fourth p-type device;
- and
- a fifth p-type device coupled to the fourth p-type device, first and second p-type devices;
- and the third resistive device.
A reference generator apparatus, comprising:
- a current mirror comprising a first n-type device and a second n-type device;
- a first bi-polar junction transistor (BJT) connected to the first n-type device;
- a first resistive device coupled in series with the second n-type device;
- a second BJT coupled to the second n-type device such that the first resistive device is connected in series with the second BJT;
- a third n-type device having a gate terminal connected to the second n-type device;
- a second resistive device coupled to the third n-type device;
- a fourth n-type device connected to the third n-type device;
- a third resistive device coupled to the fourth n-type device;
- and
- a fifth n-type device coupled to the fourth n-type device, first and second n-type devices;
- and the third resistive device.
Dependencies are inferred from the claim text.