Semiconductor device

A semiconductor device comprising:

• an external terminal;
• a switching output stage arranged to perform switching drive of a terminal voltage at the external terminal;
• a counter arranged to count the number of pulses of an input pulse signal branched to a first path so as to generate a mask signal;
• a logical gate arranged to determine according to the mask signal whether to mask the input pulse signal branched to a second path or to pass through the input pulse signal branched to the second path without masking;
• an output control unit arranged to generate a drive signal for the switching output stage according to an output signal of the logical gate;
• and
• a comparator arranged to compare a predetermined threshold value with the terminal voltage so as to generate a reset signal of the counter,
• wherein the counter increments the count value when a pulse of the input pulse signal comes and resets the count value to zero when a pulse of the reset signal comes, and switches the mask signal to a first logical level when masking is enabled at a time point when the count value reaches a first set value without being reset,
• wherein the counter continues to count the number of pulses of the input pulse signal also after the mask signal is set to the first logical level, and when the count value reaches a second set value larger than the first set value, the mask signal is switched to a second logical level when masking is canceled, and the count value is reset to zero,
• wherein
• the counter includes a first counter unit that receives input of the input pulse signal and outputs a first pulse signal whose logical level is switched when the count value reaches the first set value, a second counter unit that is connected to a post-stage of the first counter unit and outputs a second pulse signal whose logical level is switched when the count value reaches the second set value, and a D flip-flop that receives input of the first pulse signal and fixes a third pulse signal to a predetermined logical level when the logical level of the first pulse signal is switched,
• the first counter unit is reset by the reset signal and the second pulse signal,
• the second counter unit is reset by the third pulse signal,
• the D flip-flop is reset by the second pulse signal, and
• the third pulse signal or a logically inverted signal thereof is output as the mask signal.