Embedded logic analyzer and integrated circuit including the same

An embedded logic analyzer included in an integrated circuit, comprising:

• input selector circuitry configured to select as an input data signal one of logic signals from function blocks included in the integrated circuit and to provide the input data signal;
• a comparison block configured to generate a capture data signal and a plurality of comparison enable signals based on the input data signal such that the comparison enable signals are activated respectively based on different comparison conditions;
• an operation block configured to perform a logic operation on the comparison enable signals to generate a data enable signal indicating a data capture timing;
• packer circuitry configured to generate a packer data signal including capture data and capture time information based on the capture data signal, the data enable signal and a time information signal;
• and
• a main controller configured to control operations of the input selector circuitry, the comparison block, the operation block and the packer circuitry,
• wherein the packer circuitry includes:
• data extractor circuitry configured to generate data bit signals based on the capture data signal, the data bit signals each having different numbers of bits;
• time information extractor circuitry configured to generate time information bit signals based on the time information signal, the time information bit signals each having different numbers of bits;
• synthesizer circuitry configured to combine the data bit signals and the time information bit signals to generate combined data signals that each have a same number of bits;
• and
• a multiplexer configured to selectively output one of the combined data signals as the packer data signal based on a time size signal.

An embedded logic analyzer, comprising:

• first circuitry configured to,
• receive input data generated by at least one function block of an integrated circuit, and
• generate a capture data signal based on reference data signals and the input data;
• and
• second circuitry configured to generate a packer data signal including debugging information of the integrated circuit by combining capture data and capture time information based on the capture data signal and a time information signal, the debugging information including the combined capture data and capture time information,
• wherein the second circuitry includes:
• data extractor circuitry configured to generate a data bit signal of a fixed bit number based on the capture data signal;
• time information extractor circuitry configured to generate a time information bit signal of the fixed bit number based on the time information signal;
• and
• a multiplexer configured to selectively output one of the data bit signal and the time information bit signal as the packer data signal based on a time period signal.