Direct measurement test structures for measuring static random access memory static noise margin

A method for measuring a stability of a static random access memory (SRAM) cell in an integrated circuit (IC) device, comprising:

• measuring a voltage transfer curve from a first side of a test structure, wherein the first side of the test structure is electrically coupled to a first internal node of the SRAM cell on a first side of a cut off via a first transmission gate (TG);
• obtaining a butterfly curve by plotting a curve that is substantially symmetrical to the measured voltage transfer curve;
• and
• determining a static noise margin (SNM) for each of the one or more SRAM cells by measuring an area bounded by the butterfly curve, wherein:
• the cut off provides an electrical open between the first side of the cut off and a second side of the cut off;
• and
• the first internal node is electrically coupled to a first external pin through the first TG;
• and
• a second internal node at the second side of the cut off is electrically coupled to a second external pin through a second TG.

An array of test structures comprising a plurality of test structures for directly measuring a stability of a plurality of static random access memory (SRAM) cells, the array of test structures comprising:

• multiple levels of transmission gates (TGs);
• a first chip analog input/output (IO);
• and
• a second chip analog IO, wherein:
• a plurality of internal nodes of the plurality of SRAM cells are electrically coupled through the multiple levels of transmission gates (TGs) to one of the first chip analog IO and the second chip analog IO;
• and
• each test structure of the plurality of test structures is operable to address a respective one of the plurality of SRAM cells, and wherein each test structure of the plurality of test structures are operable to measure static noise margin (SNM) of a respective one of the plurality of SRAM cells.