IC with stragically biased digital circuitry
AssigneeRambus Inc.
InventorsThomas Vogelsang, Frederick A. Ware
Life of this patent
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Abstract
During operation of an IC component within a first range of temperatures, a first bias voltage is applied to a first substrate region disposed adjacent a first plurality of transistors to effect a first threshold voltage for the first plurality of transistors. During operation of the IC component within a second range of temperatures that is distinct from and lower than the first range of temperatures, a second bias voltage is applied to the first substrate region to effect a second threshold voltage for the first plurality of transistors that is at least as low as the first threshold voltage.
Claims20
A method of operating an integrated-circuit (IC) component, the method comprising:
- applying a first bias voltage to a first substrate region disposed adjacent a first plurality of transistors to effect a leakage current for the first plurality of transistors below a nominal leakage current;
- and
- applying a second bias voltage, different from the first bias voltage, to a second substrate region disposed adjacent a second plurality of transistors to effect a switching speed for the second plurality of transistors greater than a nominal switching speed.
An integrated-circuit (IC) component comprising:
- first and second pluralities of transistors;
- first and second substrate regions disposed adjacent the first plurality of transistors and the second plurality of transistors, respectively;
- and
- biasing circuitry to apply (i) a first bias voltage to the first substrate region to effect a leakage current for the first plurality of transistors below a nominal leakage current and (ii) a second bias voltage, different from the first bias voltage, to the second substrate region to effect a switching speed for the second plurality of transistors greater than a nominal switching speed.
An integrated-circuit (IC) component comprising:
- first and second pluralities of transistors;
- first and second substrate regions disposed adjacent the first plurality of transistors and the second plurality of transistors, respectively;
- and
- means for applying (i) a first bias voltage to the first substrate region to effect a leakage current for the first plurality of transistors below a nominal leakage current and (ii) a second bias voltage, different from the first bias voltage, to the second substrate region to effect a switching speed for the second plurality of transistors greater than a nominal switching speed.
Dependencies are inferred from the claim text.