Hybrid analog-digital matrix processors
AssigneeLightmatter, Inc.
InventorsTyler J. Kenney, Martin B. Z. Forsythe, Tomo Lazovich, Darius Bunandar
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Abstract
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
Claims23
A hybrid analog-digital processor comprising:
- a digital-to-analog converter (DAC) unit comprising a plurality of DACs;
- a photonic processor arranged to perform matrix-matrix multiplication or matrix-vector multiplication and coupled to outputs of the DAC unit;
- an analog-to-digital (ADC) unit comprising a plurality of ADCs and coupled to outputs of the photonic processor;
- a digital multiplicative scaling unit coupled to outputs of the ADC unit;
- and
- a digital accumulator coupled to outputs of the digital multiplicative scaling unit, wherein the digital accumulator comprises a memory unit and a digital adder.
A hybrid analog-digital processor comprising:
- a digital-to-analog converter (DAC) unit comprising a plurality of DACs;
- an analog processor arranged to perform matrix-matrix multiplication or matrix-vector multiplication and coupled to outputs of the DAC unit;
- an analog-to-digital (ADC) unit comprising a plurality of ADCs and coupled to outputs of the analog processor;
- a digital multiplicative scaling unit coupled to outputs of the ADC unit;
- and
- a digital accumulator coupled to outputs of the digital multiplicative scaling unit, wherein the digital accumulator comprises a memory unit and a digital adder.
A method of manufacturing a hybrid analog-digital processor comprising:
- forming a digital-to-analog converter (DAC) unit comprising a plurality of DACs;
- forming an analog processor arranged to perform matrix-matrix multiplication or matrix-vector multiplication and coupled to outputs of the DAC unit;
- forming an analog-to-digital (ADC) unit comprising a plurality of ADCs and coupled to outputs of the analog processor;
- forming a digital multiplicative scaling unit coupled to outputs of the ADC unit;
- and
- forming a digital accumulator coupled to outputs of the digital multiplicative scaling unit, wherein the digital accumulator comprises a memory unit and a digital adder.
Dependencies are inferred from the claim text.