Quarter-rate serial-link receiver with low-aperture-delay samplers

A serial-link receiver, comprising:

• a continuous-time linear equalizer (CTLE);
• a decision-feedback equalizer (DFE);
• a sampler;
• clock-and-data-recovery (CDR) circuits, which dynamically adjust a DFE threshold and a sampler offset, wherein the CDR circuits perform calculations to determine corresponding DFE-threshold and sampler-offset adjustments in the digital domain, and then combine the DFE-threshold and sampler-offset adjustments into a combined adjustment signal;
• and
• a digital-to-analog converter (DAC), which converts the combined adjustment signal into a corresponding analog adjustment signal, which is fed back into the serial-link receiver through a single tap.

A method for operating a low-aperture-delay sampler, comprising:

• receiving an input signal;
• receiving a clock signal;
• feeding the input signal through a first sampling channel, which samples the input signal when a clock signal is low and is associated with a previous clock phase;
• feeding the input signal through a second sampling channel, which samples the input signal when a rising edge is received in the clock signal, wherein the rising edge is associated with a present clock phase;
• and
• combining outputs of the first and second sampling channels to produce a sampler output with a significantly reduced aperture delay.

A method for operating a serial-link receiver, which includes a CTLR, a DFE, a sampler and CDR circuits, the method comprising:

• performing digital calculations to determine DFE-threshold and sampler-offset adjustments;
• combining the DFE-threshold and sampler-offset adjustments into a combined adjustment signal;
• using a DAC to convert the combined adjustment signal into a corresponding analog adjustment signal;
• and
• feeding back the analog adjustment signal into the serial-link receiver through a single tap.