Device with isolation barrier and fault detection
AssigneeTexas Instruments Incorporated
InventorsXiong Li, William Toth, Honglin Guo, Danyang Zhu
Life of this patent
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Abstract
A device that comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a first clock signal generator. The second semiconductor die comprises a fault detection circuit, the fault detection circuit comprising a second clock signal generator, a first counter coupled to the second clock signal generator, multiple storage devices coupled to the second clock signal generator and to the first counter, a logic gate coupled to the multiple storage devices, a second counter coupled to the logic gate and to the first clock signal generator, and a comparator coupled to the logic gate and the second counter.
Claims24
A device, comprising:
- a first semiconductor die comprising a first clock signal generator;
- and
- a second semiconductor die comprising a fault detection circuit, the fault detection circuit comprising:
- a second clock signal generator;
- a first counter coupled to the second clock signal generator;
- multiple storage devices coupled to the second clock signal generator and to the first counter;
- a logic gate coupled to the multiple storage devices;
- a second counter coupled to the logic gate and to the first clock signal generator;
- and
- a comparator coupled to the logic gate and the second counter.
A device, comprising:
- a first semiconductor die comprising a first clock signal generator;
- and
- a second semiconductor die comprising a fault detection circuit, the fault detection circuit comprising:
- a second clock signal generator;
- a first counter coupled to the second clock signal generator;
- multiple storage devices coupled to the second clock signal generator and to the first counter;
- a logic gate coupled to the multiple storage devices;
- a second counter coupled to the logic gate and to the first clock signal generator;
- an amplifier coupled to the second counter;
- an analog-to-digital converter (ADC) coupled to the amplifier;
- and
- another storage device coupled to the ADC.
A system, comprising:
- a power transistor;
- an isolated gate driver, a high voltage portion of the isolated gate driver is isolated from a low voltage portion of the isolated gate driver, is configured to control operation of the power transistor in response to a control signal received from the low voltage portion, and is configured to provide a clock signal to a fault detection circuit of the low voltage portion, wherein the fault detection circuit is configured to generate a fault signal in response to failing to detect the clock signal;
- and
- a controller coupled to the isolated gate driver, the controller configured to output the control signal to the low voltage portion of the isolated gate driver, to receive the fault signal from the low voltage portion of the isolated gate driver, and to interrupt delivery of power to the power transistor in response to receipt of the fault signal from the fault detection circuit.
A method, comprising:
- receiving a control signal by a low voltage portion of an isolated gate driver, the low voltage portion on a first semiconductor die;
- transmitting the control signal by the low voltage portion to a high voltage portion of the isolated gate driver, the high voltage portion on a second semiconductor die;
- driving a power transistor by the high voltage portion based on the control signal;
- generating a clock signal by the high voltage portion;
- transmitting the clock signal by the high voltage portion to the low voltage portion;
- monitoring the clock signal received from the high voltage portion by a fault detection circuit of the low voltage portion;
- and
- based on the monitoring of the clock signal, outputting a fault signal to a controller, wherein the controller is configured to control power supply to the power transistor.
Dependencies are inferred from the claim text.