Method for biasing a differential pair of transistors, and corresponding integrated circuit
AssigneeSTMicroelectronics (Rousset) SAS
InventorsYohan Joly, Vincent Binet, Michel Cuenca
Life of this patent
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Abstract
An integrated circuit includes at least one differential pair of transistors, a bias current generator that is configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of said differential pair by a respective resistive element. A compensation current generator is configured to generate a compensation current in one of the two resistive elements so as to compensate for a difference between actual values of the threshold voltages of the transistors of said differential pair.
Claims24
A method for biasing at least one differential pair of transistors in an integrated circuit, the method comprising:
- generating a bias current on a bias node that is coupled to a source terminal of each transistor of the at least one differential pair by a respective resistive element;
- and
- generating a compensation current in a first resistive element of the two resistive elements so as to compensate for a difference between actual values of threshold voltages of the transistors of the at least one differential pair.
An integrated circuit comprising:
- at least one differential pair of transistors;
- a bias current generator configured to generate a bias current on a bias node that is coupled to a source terminal of each transistor of the at least one differential pair by a respective resistive element;
- and
- a compensation current generator configured to generate a compensation current in a first resistive element of the two resistive elements so as to compensate for a difference between actual values of threshold voltages of the transistors of the at least one differential pair.
Dependencies are inferred from the claim text.