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US 10,979,036 B1Granted
Divider circuit
AssigneeDialog Semiconductor GmbH
InventorsMahbub Reja, Shobak Kythakyapuzha, Jan Prummel
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AssigneeDialog Semiconductor GmbH
InventorsMahbub Reja, Shobak Kythakyapuzha, Jan Prummel
Estimating the term…
A frequency divider is provided which uses common circuitry to switch between different duty cycle outputs. The divider has one or more memory elements with a feedback loop and which are controllable to adjust a duty cycle of an output signal. Each memory element has a first regenerative cell and a second regenerative cell, and where one of the regenerative cells is a controllable regenerative cell which can be controlled to vary the duty cycle of an output of the frequency divider circuit. The controllable regenerative cell can be selectively activated so that in a first configuration where the controllable regenerative cell is activated an output of the frequency divider circuit has a first duty cycle and in a second configuration where the controllable regenerative cell is deactivated an output of the frequency divider circuit has a second duty cycle.
A frequency divider circuit comprising one or more memory elements with a feedback loop and which are controllable to adjust a duty cycle of an output signal, wherein the or each memory element comprises a first regenerative cell and a second regenerative cell, and where one of said regenerative cells is a controllable regenerative cell which can be controlled to vary the duty cycle of an output of the frequency divider circuit.
A transceiver comprising a frequency divider circuit comprising one or more memory elements with a feedback loop and which are controllable to adjust a duty cycle of an output signal, wherein the or each memory element comprises a first regenerative cell and a second regenerative cell, and where one of said regenerative cells is a controllable regenerative cell which can be controlled to vary the duty cycle of an output of the frequency divider circuit.
A frequency division method comprising providing one or more memory elements with a feedback loop and controlling said elements to adjust a duty cycle of an output signal, wherein the or each memory element comprises a first regenerative cell and a second regenerative cell, and where one of said regenerative cells is a controllable regenerative cell which can be controlled to vary the duty cycle of an output of the frequency divider circuit.
Dependencies are inferred from the claim text.