US 10,886,899 B2 · Low-power-consumption constant-on-time timing circuit design method and timing circuit

Abstract

Provided is a low-power-consumption Constant-On-Time (COT) timing circuit design method and a timing circuit. A Resistor-Capacitor (RC) circuit is adopted for timing, to eliminate static power consumption of a timer. A specific structure includes a fourth P-channel Metal Oxide Semiconductor (MOS) transistor M4 of which a source is connected to an input voltage VIN, a gate is connected to a COT control terminal TON_CONTROL and a drain is connected with one end of a fourth resistor R4. The other end of the fourth resistor R4 is connected with one end of a fourth capacitor C4. The other end of the fourth capacitor C4 is grounded. A negative input of a comparator VCMP is connected with a reference voltage, and a positive input is connected between the fourth capacitor C4 and the fourth resistor R4.

Claims7

Dependent claims

A method for operating a Constant-On-Time (COT) timing circuit, comprising:

making a COT timing circuit that is a Resistor-Capacitor (RC) circuit, wherein the RC circuit comprises at least a first stage circuit and a second stage circuit, wherein the first stage circuit comprises a first capacitor and a first resistor, the second stage circuit comprises a second capacitor and a second resistor;
and
charging the first capacitor with a charging current in a manner that a magnitude of the charging current is equal to a magnitude of a current passing through the resistor, and the charging current and a voltage input to the RC circuit maintains a first-order correlation prior to a voltage output from the first capacitor equals a reference voltage, wherein the reference voltage is proportional to the output voltage of the RC circuit.

A low-power-consumption Constant-On-Time (COT) timing circuit, comprising:

a first stage circuit, a second stage circuit, a first inter-stage resistor disposed between the first stage circuit and the second stage circuit, and a comparator, wherein the first stage circuit comprises a first P-channel Metal Oxide Semiconductor (PMOS) transistor of which a source is connected to an input voltage, a gate is connected to a COT control terminal (TON_CONTROL), and a drain is connected with a first end of a first resistor, wherein a second end of the first resistor is connected to a first end of a first capacitor, and a second end of the first capacitor is grounded, a negative input of a comparator is connected with a reference voltage, and a positive input of the comparator is connected to a line that connects the second end of the first resistor and the first end of the first capacitor,
wherein the second stage circuit comprises a second PMOS transistor of which a source is connected to the input voltage, a gate is connected to the COT control terminal, and a drain is connected with the first end of a second resistor, wherein a second end of the second resistor is connected to the first end of a second capacitor, and the second end of the second capacitor is grounded,
wherein a first end of the first inter-stage resistor is connected to the line that connects the second end of the first resistor and the first end of the first capacitor, and a second end of the first inter-stage resistor is connected to a line that connects the second end of the second resistor and the first end of the second capacitor.

Dependencies are inferred from the claim text.

Low-power-consumption constant-on-time timing circuit design method and timing circuit

Life of this patent

Low-power-consumption constant-on-time timing circuit design method and timing circuit

Life of this patent

Abstract

Claims7