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US 10,873,483 B2Granted
Semiconductor device and memory system
AssigneeToshiba Memory Corporation
InventorsKensuke Yamamoto, Kosuke Yanagidaira
Life of this patent
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Abstract
A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.
Claims18
A semiconductor device configured to communicate with a controller, the semiconductor device comprising:
- a first chip that includes a first circuit having a first output terminal;
- and
- a second chip that includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line, wherein
- upon receipt of a first command, the first circuit calibrates an output impedance at the first output terminal through a first calibration operation, and the first circuit issues a signal indicating that the first chip is in a ready state during the first calibration operation,
- upon receipt of a second command after the first calibration operation is performed, the second circuit calibrates an output impedance at the second output terminal through a second calibration operation based on the output impedance at the first output terminal, and
- a duration of the second calibration operation is shorter than a duration of the first calibration operation.
3 more elements
A semiconductor device configured to communicate with a controller, the semiconductor device comprising:
- a first chip that includes a first circuit having a first output terminal;
- and
- a second chip that includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line, wherein
- the first chip:
- upon receipt of a first command, calibrates an output impedance at the first output terminal through a first calibration operation,
- transmits to the controller a signal indicating that the first chip is in a busy state upon starting the first calibration operation, and
- transmits to the controller a signal indicating that the first chip is in a ready state upon completion of the first calibration operation,
- the second chip:
- upon receipt of a second command after the first calibration operation is performed, calibrates an output impedance at the second output terminal through a second calibration operation based on the output impedance at the first output terminal,
- transmits to the controller a signal indicating that the second chip is in the busy state upon starting the second calibration operation, and
- transmits to the controller a signal indicating that the second chip is in the ready state upon completion of the second calibration operation, and
- a duration of the second calibration operation is shorter than a duration of the first calibration operation.
9 more elements
A semiconductor device configured to communicate with a controller, the semiconductor device comprising:
- a first chip that includes a first circuit including a first output terminal;
- and
- a second chip that includes a second circuit including a second output terminal, which is electrically connected to the first output terminal via a first signal line, wherein
- upon receipt of a first command, the first circuit calibrates an output impedance at the first output terminal through a first calibration operation,
- upon receipt of a second command after the first calibration operation is performed, the second circuit calibrates an output impedance at the second output terminal through a second calibration operation based on the output impedance at the first output terminal,
- a duration of the second calibration operation is shorter than a duration of the first calibration operation,
- the first circuit further includes:
- a first pull-up circuit having a first terminal to which a first voltage is supplied, and a second terminal electrically connected to the first output terminal, and
- a first pull-down circuit having a first terminal to which a second voltage smaller than the first voltage is supplied and a second terminal electrically connected to the first output terminal,
- the second circuit further includes:
- a second pull-up circuit having a first terminal to which the first voltage is supplied, and a second terminal electrically connected to the second output terminal,
- a second pull-down circuit having a first terminal to which the second voltage is supplied, and a second terminal electrically connected to the second output terminal, and
- a comparator having a first terminal to which a voltage of the second output terminal is supplied and a second terminal to which a third voltage between the first voltage and the second voltage is supplied, and
- the second calibration operation includes:
- a first operation during which the first pull-up circuit and the second pull-down circuit enter an ON state while the first pull-down circuit and the second pull-up circuit enter an OFF state, and
- a second operation during which the second pull-up circuit and the first pull-down circuit enter an ON state while the second pull-down circuit and the first pull-up circuit enter an OFF state.
13 more elements
A memory system comprising:
- a semiconductor device including:
- a first chip that includes a first circuit having a first output terminal, and
- a second chip that includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line;
- and
- a controller electrically connected to the first and second chips via the first signal line and configured to issue a first command and a second command after the first command, wherein
- upon receipt of the first command, the first circuit calibrates an output impedance at the first output terminal through a first calibration operation, and the first chip generates calibration result information based on a calibration result of the first calibration operation and transmits the generated calibration result information to the controller,
- upon receipt of the second command, the second circuit calibrates an output impedance at the second output terminal through a second calibration operation based on the output impedance at the first output terminal, the second calibration operation including adjusting the output impedance of the second output terminal based on the calibration result information received from the controller, and
- a duration of the second calibration operation is shorter than a duration of the first calibration operation.
5 more elements
Dependencies are inferred from the claim text.