Generating lower frequency multi-phase clocks using single high-frequency multi-phase divider
AssigneeCadence Design Systems, Inc.
InventorsJeremy Walker, Hiu Ming Lam, Mohammad Ranjbar
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Abstract
According to certain aspects, the present embodiments are directed generally to data communication systems, and more particularly to generating multi-phase clocks in a SerDes system. Embodiments provide SerDes components and methods that are capable of generating multiple different sampling frequencies for parallelizing serial data from a single high speed clock. These and other embodiments can be implemented with circuits that are relatively small and low-power as compared to conventional approaches.
Claims17
A serializer-deserializer transceiver, comprising:
- an initial divider that receives an input clock having a first frequency, wherein the initial divider comprises a plurality of series-interconnected latches all clocked by the input clock, and wherein each of the latches produces a respective one of a plurality of first clocks, each of the first clocks having a second frequency that is a first integer fraction of the first frequency and being spaced apart in time from each other by a first phase spacing that less than one period of the first frequency by operation of the series-interconnected latches all being clocked by the input clock;
- and
- a subsequent divider that is coupled to receive and combine the plurality of first clocks from the plurality of series-interconnected latches of the initial divider to thereby produce a plurality of second clocks, each of the second clocks having a third frequency that is a second integer fraction of the second frequency.
A method for generating sampling clocks in a serializer-deserializer transceiver, comprising:
- receiving an input clock having a first frequency;
- initially dividing the input clock to simultaneously produce a plurality of first clocks, each of the first clocks having a second frequency that is a first integer fraction of the first frequency and being spaced apart in time from each other by a first phase spacing that less than one period of the first frequency, wherein initially dividing comprises obtaining each of the plurality of first clocks from a respective one of a series of interconnected latches, wherein all of the latches are clocked by the input clock;
- and
- subsequently producing, by receiving and combining the plurality of first clocks from the series of interconnected latches of the initial divider, a plurality of second clocks, each of the second clocks having a third frequency that is a second integer fraction of the second frequency.
Dependencies are inferred from the claim text.