Capacitor array, successive approximation register analog-to-digital converter and capacitor array board

A capacitor array for an analog-to-digital converter, comprising a control logic generation circuit, a control code logic conversion circuit, a first sub-capacitor array and a second sub-capacitor array that are configured to form different regions of a high-order bit region and a low-order bit region;

• wherein:
• the first sub-capacitor array comprises a plurality of first capacitor units and a plurality of first switches, the plurality of first capacitor units are sequentially arranged according to binary weighted capacitances from a least significant bit to a most significant bit, the plurality of first capacitor units are connected in parallel;
• each of the plurality of first capacitor units is connected to the control logic generation circuit via one of the plurality of first switches;
• the control logic generation circuit is configured to output a first binary code corresponding to the first sub-capacitor array to the plurality of first switches, to control switching states of the plurality of first switches;
• the second sub-capacitor array comprises a plurality of second capacitor units arranged in parallel and a plurality of second switches, each of the plurality of second capacitor units is connected to the control code logic conversion circuit via one of the plurality of second switches;
• the control code logic conversion circuit is connected to the control logic generation circuit;
• capacitances of the plurality of second capacitor units are equal;
• the control logic generation circuit is configured to output a second binary code corresponding to the second sub-capacitor array;
• the control code logic conversion circuit is configured to convert the second binary code to a thermometer code, and output the thermometer code to the plurality of second switches, to control switching states of the plurality of second switches.