Divider control and reset for phase-locked loops

A method, comprising:

• initiating a frequency calibration operation for a phase-locked loop circuit that includes a programmable divider circuit comprising a plurality of divider stages;
• in response to initiating the frequency calibration operation:
• generating, by a divider control circuit comprising a plurality of flip-flop circuits, a timing signal based on respective output signals of at least two divider stages of the plurality of divider stages, wherein the timing signal is generated in response to determining that one or more divider stages of the plurality of divider stages have reached a particular logic state;
• and
• toggling at least one of the plurality of flip-flop circuits using the timing signal to generate a pause signal;
• maintaining the particular logic state by holding the one or more divider stages using the pause signal;
• and
• releasing the one or more divider stages from the particular logic state upon completing the frequency calibration operation.

An apparatus, comprising:

• an oscillator circuit configured to generate an oscillator signal, wherein a frequency of the oscillator signal is based on a voltage level of a control signal;
• a programmable divider circuit including a plurality of divider stages, wherein the programmable divider circuit is configured to generate a divided signal using the oscillator signal, wherein a frequency of the divided signal is less than the frequency of the oscillator signal, wherein a given one of the plurality of divider stages is configured to change a frequency divisor in response to a control signal;
• a phase detector circuit configured to compare a reference signal and the divided signal;
• a charge pump circuit configured to modify, based on a result of a comparison of the reference signal and the divided signal, the voltage level of the control signal;
• a control circuit configured to:
• during a frequency calibration operation:
• deactivate the programmable divider circuit, the phase detector circuit, and the charge pump circuit;
• and
• hold one or more divider stages of the plurality of divider stages in a particular logic state;
• and
• in response to a completion of the frequency calibration operation, reactivate the programmable divider circuit, phase detector circuit, and the charge pump circuit based on a comparison of respective phases of the reference signal and the divided signal.