Clamp logic circuit
AssigneeRichWave Technology Corp.
InventorsChih-Sheng Chen, Tien-Yun Peng
Life of this patent
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Abstract
A clamp logic circuit has a logic circuit, a control terminal, a current clamp circuit and an output terminal. The logic circuit has at least a junction field-effect transistor (JFET). The control terminal receives an input signal. The current clamp circuit has a transistor and a resistor. A first end of the transistor is coupled to the control terminal, a second end of the transistor is coupled to a first end of the resistor, a control end of the transistor is coupled to a reference voltage, and a second end of the resistor is coupled to an input end of the logic circuit. The output terminal is coupled to an output end of the logic circuit.
Claims20
A clamp logic circuit, comprising:
- a logic circuit, comprising at least a junction field-effect transistor (JFET);
- a control terminal, configured to receive an input signal;
- a current clamp circuit, configured to limit a maximum of a current flowing from the control terminal into the current clamp circuit to be less than a predetermined value when an external alternating current (AC) signal is transmitted to the control terminal, the current clamp circuit comprising a first transistor and a first resistor, a first end of the first transistor being coupled to the control terminal, a second end of the first transistor being coupled to a first end of the first resistor, a control end of the first transistor being coupled to a reference voltage, and a second end of the first resistor being coupled to an input end of the logic circuit;
- and
- an output terminal, coupled to an output end of the logic circuit.
Dependencies are inferred from the claim text.