Semiconductor device including charge pump circuit

A semiconductor device comprising:

• a charge pump circuit for generating an output voltage by pumping an input voltage according to a first main clock and a second main clock;
• a voltage detection circuit for generating a comparison signal by comparing the output voltage with a reference voltage;
• and
• a driving control circuit for generating the first main clock and the second main clock according to a first external clock and a second external clock during an activation time period of the comparison signal while controlling a transition sequence such that the second main clock transitions to a logic high level or to a logic low level after the first main clock respectively transitions to a logic high level or to a logic low level,
• wherein the activation time period is a time period during which the comparison signal is set to a logic high level by the voltage detection circuit,
• wherein the charge pump circuit includes two or more pump stages coupled in series, and
• wherein the charge pump circuit drives odd-numbered pump stages according to the first main clock and a first sub clock which is an inverted signal of the first main clock, and drives even-numbered pump stages according to the second main clock and a second sub clock which is an inverted signal of the second main clock.

An operating method of a semiconductor device, comprising:

• Generating a first main clock and a second main clock by respectively latching a first external clock and a second external clock according to an output enable signal;
• generating an output voltage by pumping an input voltage according to the first main clock and the second main clock;
• generating a comparison signal by comparing the output voltage with a reference voltage;
• and
• generating the output enable signal by determining whether a transition sequence of the first external clock and the second external clock meets a condition during an activation time period of the comparison signal,
• wherein the generating of the output enable signal includes:
• storing the first main clock and the second main clock as a first preliminary clock and a second preliminary clock, respectively, at an end of the activation time period of the comparison signal;
• decoding the logic levels of the first preliminary clock and the second preliminary clock to generate a selection signal;
• according to the selection signal, selecting one of the first external clock and an inverted signal of the first external clock to output a first sequence selection signal, and selecting one of the second external clock and an inverted signal of the second external clock to output a second sequence selection signal;
• and
• generating the output enable signal according to the comparison signal, the first sequence selection signal and the second sequence selection signal.

An operating method of a semiconductor device, comprising:

• generating a first main clock and a second main clock by respectively latching a first external clock and a second external clock according to an output enable signal;
• generating an output voltage by pumping an input voltage according to the first main clock and the second main clock;
• generating a comparison signal by comparing the output voltage with a reference voltage;
• and
• generating the output enable signal by determining whether a transition sequence of the first external clock and the second external clock meets a condition during an activation time period of the comparison signal,
• wherein the generating of an output voltage by pumping an input voltage according to the first main clock and the second main clock includes
• driving odd-numbered pump stages according to the first main clock and a first sub clock which is an inverted signal of the first main clock;
• and
• driving even-numbered pump stages according to the second main clock and a second sub clock which is an inverted signal of the second main clock.