Low dropout regulator with smart offset

A low-dropout (LDO) regulator, comprising:

• a pass transistor;
• a charge pump connected to the pass transistor;
• and
• an error amplifier connected through the charge pump to the pass transistor, wherein the error amplifier receives a voltage VO from the pass transistor and generates a voltage VE based on the voltage VO and a reference voltage;
• and
• wherein the charge pump receives the voltage VE from the error amplifier, generates a voltage VE* that is lower than VE by an offset and supplies the voltage VE* as a gate voltage to the pass transistor,
• wherein the charge pump includes a fast-switched capacitor charge pump network, and
• wherein the fast-switched capacitor charge pump network operates on non-overlapping phases Φ1 and Φ2 generated by a ring oscillator coupled to a non-overlapping clock generator.

A negative voltage offset low-dropout (NVO-LDO) regulator, comprising:

• a pass transistor;
• and
• a negative voltage offset circuit connected to the pass transistor, wherein the negative voltage offset circuit receives an error voltage VE, forms an offset error voltage VE*, and applies the offset error voltage VE* to a gate of the pass transistor, wherein forming includes operating four switched capacitors A-D during two non-overlapping phases, Φ1 and Φ2 such that:
• during phase Φ1, capacitor A gets charged to the error voltage VE, capacitor B gets charged to VDD/2 and capacitors C and D get charged to 0.5V, and
• during phase Φ2, all the capacitors are connected in series with the capacitors C and D having opposite polarity.

A negative voltage offset low-dropout (NVO-LDO) regulator, comprising:

• a pass transistor;
• and
• a charge pump connected to the pass transistor, wherein the charge pump includes four switched capacitors A-D and wherein the charge pump:
• receives an error voltage VE;
• forms an offset error voltage VE*, wherein forming includes operating the four switched capacitors A-D in the charge pump during two non-overlapping phases, Φ1 and Φ2, such that:
• during phase Φ1, capacitor A gets charged to the error voltage VE, capacitor B gets charged to VDD/2 and capacitors C and D get charged to ≈0.5V, and
• during phase Φ2, all the capacitors are connected in series with the capacitors C and D having opposite polarity;
• and
• applies the offset error voltage VE* to a gate of the pass transistor.

In an LDO regulator having a supply voltage VDD, a method, comprising:

• receiving an error voltage VE;
• and
• generating an offset error voltage VE* from the error voltage VE, wherein generating includes operating a charge pump having four switched capacitors A-D using a clock having two non-overlapping phases, Φ1 and Φ2, such that:
• during phase Φ1, capacitor A gets charged to the error voltage VE, capacitor B gets charged to VDD/2 and capacitors C and D get charged to 0.5V, and
• during phase Φ2, all the capacitors are connected in series with the capacitors C and D having opposite polarity.

An LDO regulator, comprising:

• a pass transistor connected to an LDO supply voltage VDD;
• and
• an offset module connected to the pass transistor, wherein the offset module receives an error voltage VE, and provides a voltage VE* to a gate of the pass transistor, wherein VE*=VE-VOS, where VOS=A-A×VDD, where A is a number greater than zero and less than one,
• wherein the offset module includes a charge pump having four capacitors A-D operating during two non-overlapping phases, Φ1 and Φ2,
• wherein during phase Φ1 capacitor A is charged to approximately VE capacitor B is charged to approximately A×VDD and capacitors C and D are charged to approximately A Volts, and
• wherein during phase Φ2 all the capacitors are connected in series with the capacitors C and D having opposite polarity.