Discharge control method for bus capacitor in power converter

A discharge control method for a bus capacitor in a power converter including a bridge arm and the bus capacitor connected in parallel, wherein the bridge arm includes a first power semiconductor switch group, a second power semiconductor switch group, a third power semiconductor switch group and a fourth power semiconductor switch group, the bus capacitor includes a first bus capacitor and a second bus capacitor which are connected in series, and the first power semiconductor switch group, the second power semiconductor switch group, the third power semiconductor switch and the fourth power semiconductor switch group are connected in series and then are connected in parallel to a positive terminal of the first bus capacitor and a negative terminal of the second bus capacitor;

• the power converter further comprises a fifth power semiconductor switch group and a sixth power semiconductor switch group, the fifth power semiconductor switch group and the sixth power semiconductor switch group forming a series branch, one end of the series branch being connected to a connection point of the first bus capacitor and the second bus capacitor, and the other end of the series branch being connected to a connection point of the second power semiconductor switch group and the third power semiconductor switch group;
• and wherein the method comprises:
• judging a working state of the power converter and a connection state of the power converter to outside by a controller, and outputting a plurality of pulse control signals to the corresponding plurality of power semiconductor switch groups when the working state of the power converter is in a discharge state and the power converter is disconnected from outside;
• and
• controlling ON and OFF of the plurality of power semiconductor switch groups respectively by the plurality of pulse control signals, such that the bus capacitor and the power semiconductor switch groups in an ON state form a discharge loop between the positive terminal and the negative terminal of the bus capacitor within at least one preset time, thereby causing the bus capacitor to discharge and causing the electric energy of the bus capacitor to be consumed in the power semiconductor switch groups in an ON state, wherein the at least one preset time includes a first preset time and a second preset time;
• the plurality of pulse control signals include a first pulse control signal, a second pulse control signal, a third pulse control signal, a fourth pulse control signal, a fifth pulse control signal and a sixth pulse control signal for controlling the ON and OFF of the first power semiconductor switch group, the second power semiconductor switch group, the third power semiconductor switch group, the fourth power semiconductor switch group, the fifth power semiconductor switch group and the sixth power semiconductor switch group, respectively, so as to form the discharge loop among the first bus capacitor, the first power semiconductor switch group, the second power semiconductor switch group, the fifth power semiconductor switch group and the sixth power semiconductor switch group during the first preset time, and to form the discharge loop among the second bus capacitor, the fifth power semiconductor switch group, the sixth power semiconductor switch group, the third power semiconductor switch group and the fourth power semiconductor switch group during the second preset time.

A discharge control method for a bus capacitor in a power converter, wherein the bridge arm includes a first power semiconductor switch group, a second power semiconductor switch group, a third power semiconductor switch group and a fourth power semiconductor switch group, the bus capacitor includes a first bus capacitor and a second bus capacitor which are connected in series, and the first power semiconductor switch group, the second power semiconductor switch group, the third power semiconductor switch and the fourth power semiconductor switch group are connected in series and then are connected in parallel to a positive terminal of the first bus capacitor and a negative terminal of the second bus capacitor;

• the power converter further comprises a first capacitor group, one end of the first capacitor group being connected to a connection point of the first power semiconductor switch group and the second power semiconductor switch group, and the other end of the first capacitor group being connected to a connection point of the third power semiconductor switch group and the fourth power semiconductor switch group;
• wherein the method comprises:
• judging a working state of the power converter and a connection state of a main circuit brcaker in the power converter to outside by a controller, and outputting a plurality of pulse control signals to the corresponding plurality of power semiconductor switch groups when the working state of the power converter is in a discharge state and the power converter is disconnected from outside;
• and
• controlling ON and OFF of the plurality of power semiconductor switch groups respectively by the plurality of pulse control signals, such that the bus capacitor and the power semiconductor switch groups in an ON state form a discharge loop between the positive terminal and the negative terminal of the bus capacitor within at least one preset time, thereby causing the bus capacitor to discharge and causing the electric energy of the bus capacitor to be consumed in the power semiconductor switch groups in an ON state,
• wherein the at least one preset time includes a first preset time and a second preset time;
• the plurality of pulse control signals include a first pulse control signal, a second pulse control signal, a third pulse control signal and a fourth pulse control signal for controlling the ON and OFF of the first power semiconductor switch group, the second power semiconductor switch group, the third power semiconductor switch group and the fourth power semiconductor switch group, respectively, so as to form the discharge loop among the first capacitor group, the second power semiconductor switch group and the third power semiconductor switch group during the first preset time, and to form the discharge loop among the first bus capacitor, the first power semiconductor switch group, the first capacitor group, the fourth power semiconductor switch group and the second bus capacitor during the second preset time.