Zero cost NVM cell using high voltage devices in analog process
AssigneeJonker LLC
InventorDavid Liu
Life of this patent
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Abstract
A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate and a drift region to impart a programming voltage. Programming is effectuated using a drain extension which can act to inject hot electrons. The cell can be operated as a one-time programmable (OTP) or multiple-time programmable (MTP) device. The fabrication of the cell relies on processing steps associated with high voltage devices, thus avoiding the need for additional masks, manufacturing steps, etc.
Claims20
A method of forming a programmable non-volatile memory device in a high voltage circuit portion of a substrate comprising:
- forming a floating gate on a surface of the high voltage circuit portion of a substrate;
- forming a source region in the high voltage circuit portion of a substrate;
- forming a drain region in the high voltage circuit portion of a substrate;
- forming a drift region with a first portion overlapping part of said drain region and a second portion overlapping part of said floating gate in a direction perpendicular to the substrate, the drift region comprising a notch extending into the drift region in a direction away from the source region;
- wherein the drain region has an extension protruding from the drain region into the notch and overlapping a first edge of the floating gate in a direction perpendicular to the substrate, an electron infection region is formed by said drain extension and said first edge of said floating gate, and the notched drift region overlaps a sufficient portion of the floating gate such that a programming voltage for the device can be imparted to said floating gate through areal capacitive coupling.
A method of forming a programmable non-volatile memory device in a high voltage circuit portion of a substrate comprising;
- forming a floating gate on a surface of the high voltage circuit portion of a substrate;
- forming a source for the device in the high voltage circuit portion of a substrate;
- forming a drain for the device in the high voltage circuit portion of a substrate;
- forming a drift region also having said first impurity type with a first portion overlapping part of said drain and a second portion overlapping part of said floating gate in a direction perpendicular to the substrate, the drift region comprising a notch extending into the drift region in a direction away from the source region;
- wherein the drain region has an extension protruding from the drain region into the notch and overlapping a first edge of the floating gate in a direction perpendicular to the substrate, an injection region having a first impurity type formed by said drain extension abutting said first edge of said floating gate is adapted to permit programming of the device through channel hot electron injection to said floating gate, and the drift region overlaps a sufficient portion of the floating gate such that a programming voltage for the device can be imparted to said floating gate through areal capacitive coupling.
A method of forming a programmable non-volatile memory device in a high voltage circuit portion of a substrate comprising;
- forming a floating gate on a surface of the high voltage circuit portion of a substrate;
- forming a source region in the high voltage circuit portion of a substrate;
- forming an N-type drain region in the high voltage circuit portion of a substrate;
- forming an N-type drift region with a notch extending into the drift region in a direction away from the source region, and such that a first portion of said N-type drift region overlaps part of said N-type drain region and a second portion of said N-type drift region overlaps part of said floating gate in a direction perpendicular to the substrate;
- wherein the drain region has an extension protruding from the drain region into the notch and overlapping a first edge of the floating gate in a direction perpendicular to the substrate, an injection region having a first impurity type formed by said drain extension abutting said first edge of said floating gate is adapted to permit programming of the device through channel hot electron injection to said floating gate, and said second portion of said N-type drift region overlaps a sufficient portion of the floating gate such that a programming voltage for the device can be imparted to said floating gate through areal capacitive coupling to said N-type drain region;
- further wherein the programmable non-volatile memory device as formed does not include or require a control gate to operate.
Dependencies are inferred from the claim text.