Spacer structures for a transistor device

An integrated circuit product, comprising:

• a final gate structure for a transistor device;
• a gate cap positioned above said final gate structure, said final gate structure comprising first and second opposing sidewalls;
• first and second source/drain regions formed in a semiconductor substrate, wherein said first and second source/drain regions are respectively, positioned adjacent said first and second opposing sidewalls, respectively, of said final gate structure;
• a low-k sidewall spacer positioned on and in contact with said first and second opposing sidewalls of said final gate structure;
• a first and a second contact etch stop layer (CESL) wherein said first and second CESLs, are, respectively, positioned adjacent said first and second opposing sidewalls, respectively, said first and second CESLs being positioned on and in contact with said low-k sidewall spacer, wherein each of said first and second CESLs comprises a first substantially horizontally oriented upper surface and wherein an upper portion of each of said first and second CESLs comprises a second substantially horizontally oriented surface and a substantially vertically oriented surface;
• and
• a high-k spacer positioned on and in contact with said second substantially horizontally oriented surface and said substantially vertically oriented surface of said first and second CESLs.

An integrated circuit product, comprising:

• a final gate structure for a transistor device;
• a gate cap positioned above said final gate structure, said final gate structure comprising first and second opposing sidewalls;
• first and second source/drain regions formed in a semiconductor substrate, wherein said first and second source/drain regions are, respectively, positioned adjacent said first and second opposing sidewalls, respectively, of said final gate structure;
• a low-k sidewall spacer positioned on and in contact with said first and second opposing sidewalls of said final gate structure;
• a first and a second contact etch stop layer (CESL) wherein said first and second CESLs are, respectively, positioned adjacent said first and second opposing sidewalls, respectively, of said final gate structure, said first and second CESLs being positioned on and in contact with said low-k sidewall spacer, wherein each of said first and second CESLs comprises a first substantially horizontally oriented upper surface, an upper portion and a lower portion positioned below said upper portion, wherein said upper portion of each of said first and second CESLs comprises a second substantially horizontally oriented surface and a substantially vertically oriented surface;
• and
• a high-k spacer positioned on and in contact with said second substantially horizontally oriented surface and said substantially vertically oriented surface of said first and second CESLs and wherein said first substantially horizontally oriented upper surface of said first and second CESLs is not contacted by said high-k spacer and wherein an outer surface of said lower portion of said first and second CESLs is not contacted by said high k spacer.