Transistor arrangement with a load transistor and a sense transistor

An electronic circuit, comprising:

• a transistor arrangement comprising:
• a drift and drain region arranged in a semiconductor body and each connected to a drain node;
• a plurality of load transistor cells each comprising a source region integrated in a first region of the semiconductor body;
• a plurality of sense transistor cells each comprising a source region integrated in a second region of the semiconductor body;
• a first source node electrically connected to the source region of each of the plurality of the load transistor cells via a first source conductor having a first area specific resistance;
• and
• a second source node electrically connected to the source region of each of the plurality of the sense transistor cells via a second source conductor having a second area specific resistance,
• wherein a second area specific resistance of the second source conductor is greater than a first area specific resistance of the first source conductor,
• wherein the first area specific resistance is given by a resistance of the first source conductor multiplied with an overall area of the first region, and wherein the second area specific resistance is given by a resistance of the second source conductor multiplied an overall area of the second region;
• and
• a regulator connected to the first source node and the second source node and configured to regulate an electric potential at the second source node such that the electric potential at the second source node essentially equals an electric potential at the first source node.