Semiconductor device

A semiconductor device, comprising:

• a first fin field effect transistor comprising a first semiconductor fin, a first gate overlapped with the first semiconductor fin, a first dielectric layer, and a pair of first spacers disposed on sidewalls of the first gate, wherein the first dielectric layer comprises first dielectric portions covered by the pair of first spacers, the first dielectric portions cover first portions of the semiconductor fin, the first dielectric layer comprises a second dielectric portion covered by the first gate, the second dielectric portion covers a second portion of the semiconductor fin, and the second portion of the semiconductor fin is located between the first portions of the semiconductor fin;
• and
• a second fin field effect transistor comprising a second semiconductor fin, a second gate overlapped with the second semiconductor fin, a second dielectric layer, and a pair of second spacers, wherein the first dielectric layer comprises third dielectric portions covered by the pair of second spacers, the third dielectric portions of the first dielectric layer cover third portions of the semiconductor fin, the second dielectric layer covers a fourth portion of the semiconductor fin, and the second dielectric layer is between the second gate and the pair of second spacers, the fourth portion of the semiconductor fin is located between the third portions of the semiconductor fin, the first dielectric layer is thinner than the second dielectric layer, and a width of the first gate is smaller than that of the second gate.

A semiconductor device, comprising:

• a semiconductor fin comprising a first channel portion and a second channel portion;
• a first gate overlapped with the first channel portion of the semiconductor fin;
• a first dielectric layer covering the first channel portion of the semiconductor fin, the first dielectric layer being between the first gate and the first channel portion of the semiconductor fin;
• a pair of first spacers disposed on the first dielectric layer and covering sidewalls of the first gate, wherein first dielectric portions of the first dielectric layer are covered by the pair of first spacers;
• a second dielectric layer covering the second channel portion of the semiconductor fin, the second channel portion being uncovered by the first dielectric layer, and the first dielectric layer being thinner than the second dielectric layer;
• a second gate disposed on the second dielectric layer and overlapped with the second channel portion of the semiconductor fin, a width of the first gate being smaller than that of the second gate;
• and
• a pair of second spacers disposed on the first dielectric layer, wherein the second dielectric layer is disposed between the pair of second spacers to space apart the second gate from the pair of second spacers, second dielectric portions of the first dielectric layer are covered by the pair of second spacers, and the second dielectric layer is in contact with the second dielectric portions of the first dielectric layer.