Method of forming semiconductor structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
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Abstract
A method of forming a semiconductor structure includes forming a dummy gate feature over a semiconductive fin; forming a first spacer around the dummy gate feature and a second spacer around the first spacer; replacing the dummy gate feature with a metal gate feature; after replacing the dummy gate feature with the metal gate feature, partially removing the second spacer such that a top of the second spacer is lower than a top of the first spacer; and depositing a capping layer over and in contact with the metal gate feature and the first spacer.
Claims20
A method, comprising:
- forming a dummy gate feature over a semiconductive fin;
- forming a first spacer around the dummy gate feature and a second spacer around the first spacer;
- replacing the dummy gate feature with a metal gate feature;
- after replacing the dummy gate feature with the metal gate feature, partially removing the second spacer such that a top of the second spacer is lower than a top of the first spacer;
- and
- depositing a capping layer over and in contact with the metal gate feature and the first spacer.
A method, comprising:
- forming a dummy gate feature over a semiconductive fin;
- forming a first spacer around the dummy gate feature;
- depositing a contact etch stop layer over the dummy gate feature and the first spacer;
- depositing an interlayer dielectric layer over the contact etch stop layer;
- removing a portion of the interlayer dielectric layer and a first portion of the contact etch stop layer to expose a top of the dummy gate feature;
- replacing the dummy gate feature with a metal gate feature;
- and
- after replacing the dummy gate feature with the metal gate feature, etching the contact etch stop layer to form a void between the first spacer and the interlayer dielectric layer.
A method, comprising:
- forming a dummy gate feature over a channel region of a semiconductive fin;
- forming a first spacer around the dummy gate feature and a second spacer around the first spacer;
- forming source and drain features in the semiconductive fin;
- forming an interlayer dielectric layer around the dummy gate feature and over the source and drain features;
- replacing the dummy gate feature with a metal gate feature;
- etching the second spacer between the first spacer and the interlayer dielectric layer;
- and
- after etching the second spacer, depositing a capping layer over and in contact with the first spacer and the interlayer dielectric layer.
Dependencies are inferred from the claim text.