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US 10,872,961 B2Granted
Semiconductor device and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHan-Pin Chung
Life of this patent
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Abstract
A method of fabricating a semiconductor device includes forming a plurality of semiconductor fins on a substrate. A liner layer is deposited on the semiconductor fins and on the substrate conformally. The semiconductor fins are patterned to form a plurality of active regions on the substrate after the liner layer is deposited.
Claims20
A method comprising:
- forming a first semiconductive fin on a substrate;
- depositing a liner layer on the first semiconductive fin and on the substrate conformally;
- after depositing the liner layer, etching a first portion of the liner layer and a portion of the first semiconductive fin to separate the first semiconductive fin into second and third semiconductive fins on the substrate, wherein after etching the first semiconductive fin, each of the second and third semiconductive fins have first and second sidewalls that remain covered by the liner layer, and an end sidewall exposed by the liner layer;
- forming an isolation layer on the end sidewall of each of the second and third semiconductive fins and on the liner layer so that it extends along the first and second sidewalls of each of the second and third semiconductive fins;
- recessing the isolation layer, such that a top portion of the end sidewall of each of the second and third semiconductive fins is exposed and an isolation structure is formed between bottom portions of the second and third semiconductive fins;
- after recessing the isolation layer, forming a first dummy gate structure and a second dummy gate structure respectively on a portion of the second semiconductive fin and a portion of the third semiconductive fin;
- and
- replacing the first and second dummy gate structures respectively with first and second metal gate structures.
5 more elements
A method comprising:
- depositing a liner layer on a first semiconductive fin and on a substrate conformally;
- after depositing the liner layer, removing a portion of the first semiconductive fin and a portion of the liner layer thereon, such that the first semiconductive fin is separated into second and third semiconductive fins, wherein the second and third semiconductive fins are end-to-end arranged on the substrate, and after etching the first semiconductive fin, each of the second and third semiconductive fins have first and second sidewalls that remain covered by the liner layer, and a first end sidewall exposed by the liner layer;
- depositing a dielectric material on the first end sidewall of each of the second and third semiconductive fins and on the liner layer so that it extends along the first and second sidewalls of each of the second and third semiconductive fins;
- and
- recessing the dielectric material, such that a portion of the first end sidewall of each of the second and third semiconductive fins is exposed and an isolation structure is formed between bottom portions of the second and third semiconductive fins.
2 more elements
A method comprising:
- forming a first semiconductive fin on a substrate, wherein the first semiconductive fin has a top surface and sidewalls;
- depositing a liner layer on the top surface and the sidewalls of the first semiconductive fin;
- etching a first portion of the liner layer and a portion of the first semiconductive fin, such that the first semiconductive fin is separated into second and third semiconductive fins, and second and third portions of the liner layer remain respectively on first and second sidewalls of the second and third semiconductive fins and the liner layer exposes an end sidewall of the second and third semiconductive fins;
- depositing a dielectric material on the end sidewall of each of the second and third semiconductive fins and on the second and third portions of the liner layer so that it extends along the first and second sidewalls of each of the second and third semiconductive fins;
- and
- after etching the first portion of the liner layer and the portion of the first semiconductive fin, etching an upper portion of the dielectric material and upper sub-portions of the second and third portions of the liner layer, such that upper portions of the end sidewall of each of the second and third semiconductive fins are exposed.
3 more elements
Dependencies are inferred from the claim text.