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US 10,872,903 B2Granted
Three dimensional memory and methods of forming the same
AssigneeMicron Technology, Inc.
InventorsSanh D. Tang, John K. Zahurak
Life of this patent
Estimating the term…
Abstract
Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.
Claims20
An apparatus comprising:
- conductive pillars extending outward from a substrate;
- memory cell strings, each of the memory cell strings is formed over a respective conductive pillar of the conductive pillars;
- a first control gate formed in a first device level, the memory cell strings including a memory cell string, the memory cell string including a first memory cell having a memory element formed in a cavity of the first control gate;
- a second control gate formed in a second device level, the memory cell string including a second memory cell having a memory element formed in a cavity of the second control gate;
- and
- a conductive channel extending between the first memory cell and the second memory cell and electrically coupled to a conductive pillar of the conductive pillars.
3 more elements
An apparatus comprising:
- a first conductive pillar and a second conductive pillar extending outward from a substrate;
- a first data line coupled to the first and second conductive pillars, the first data line located between the first and second conductive pillars and the substrate;
- a third conductive pillar and a fourth conductive pillars extending outward from the substrate;
- a second data line coupled to the third and fourth conductive pillars, the second data line located between the third and fourth conductive pillars and the substrate;
- a first memory cell string formed over the first conductive pillar;
- a second memory cell string formed over the second conductive pillar;
- a third memory cell string formed over the third conductive pillar;
- a fourth memory cell string formed over the fourth conductive pillar;
- a first control gate formed in a first device level;
- a second control gate formed in a second device level, wherein,
- the first memory cell string includes a first memory cell having a memory element formed in a first cavity of the first control gate, and a second memory cell having a memory element formed in a first cavity of the second control gate;
- the second memory cell string includes a third memory cell having a memory element formed in a second cavity of the first control gate, and a fourth memory cell having a memory element formed in a second cavity of the second control gate;
- the third memory cell string includes a fifth memory cell having a memory element formed in a third cavity of the first control gate, and a sixth memory cell having a memory element formed in a third cavity of the second control gate;
- and
- the fourth memory cell string includes a seventh memory cell having a memory element formed in a fourth cavity of the first control gate, and an eighth memory cell having a memory element formed in a fourth cavity of the second control gate.
12 more elements
An apparatus comprising:
- a first conductive pillar and a second conductive pillar extending outward from a substrate;
- a third conductive pillar and a fourth conductive pillars extending outward from the substrate;
- a region including a conductive material, the region coupled to the first, second, third, and fourth conductive pillars, the region located between substrate and the first, second, third, and fourth conductive pillars;
- a first memory cell string formed over the first conductive pillar;
- a second memory cell string formed over the second conductive pillar;
- a third memory cell string formed over the third conductive pillar;
- a fourth memory cell string formed over the fourth conductive pillar;
- a first data line coupled to the first and second memory cell strings, the first and second memory cell strings located between the first data line and the substrate;
- a second data line coupled to the third and fourth memory cell strings, the third and fourth memory cell strings located between the second data line and the substrate;
- a first control gate formed in a first device level;
- a second control gate formed in a second device level, wherein,
- the first memory cell string includes a first memory cell having a memory element formed in a first cavity of the first control gate, and a second memory cell having a memory element formed in a first cavity of the second control gate;
- the second memory cell string includes a third memory cell having a memory element formed in a second cavity of the first control gate, and a fourth memory cell having a memory element formed in a second cavity of the second control gate;
- the third memory cell string includes a fifth memory cell having a memory element formed in a third cavity of the first control gate, and a sixth memory cell having a memory element formed in a third cavity of the second control gate;
- and
- the fourth memory cell string includes a seventh memory cell having a memory element formed in a fourth cavity of the first control gate, and an eighth memory cell having a memory element formed in a fourth cavity of the second control gate.
13 more elements
Dependencies are inferred from the claim text.