Embedded non-volatile memory device and fabrication method of the same

A method of fabricating a semiconductor device, comprising:

• forming a split-gate memory cell in a first region of a substrate, further comprising;
• depositing a memory gate (MG) polysilicon layer overlying a charge trapping layer in the first region and a second region;
• patterning at least the MG polysilicon layer to form an MG in the first region;
• depositing a select gate (SG) polysilicon layer overlying an SG oxide layer and the MG in the first region and the second region;
• planarizing the SG polysilicon layer such that top surfaces of the MG and SG polysilicon layer are substantially coplanar and parallel to a surface of the substrate in the first region, wherein planarizing the SG polysilicon layer concurrently removes the SG polysilicon layer completely in the second region;
• and
• removing portions of the SG polysilicon layer and SG oxide layer in the first region to form an SG adjacent to the MG, and the SG polysilicon layer completely in the second region;
• after planarizing the SG polysilicon layer, removing the MG polysilicon layer in the second region;
• and
• forming a logic field-effect transistor (FET) including comprising a metal gate disposed over a high-K dielectric in the second region of the substrate, wherein the logic FET and the split-gate memory cell have a substantial same height.

A method to fabricate a semiconductor device, comprising:

• depositing a memory gate (MG) polysilicon layer overlying a charge trapping layer in first and second regions of a substrate;
• patterning at least the MG polysilicon layer to form an MG in the first region;
• depositing a select gate (SG) polysilicon layer overlying an SG oxide layer and the MG in the first region and the second region;
• planarizing the SG polysilicon layer such that top surfaces of the MG and the SG polysilicon layer are substantially co-planar in the first region;
• removing the SG polysilicon layer completely in the second region concurrently with planarizing the SG polysilicon layer in the first region;
• after removing the SG polysilicon layer, removing the MG polysilicon layer in the second region;
• depositing a high-k dielectric layer over the substrate in the second region, and a sacrificial polysilicon gate layer overlying the high-k dielectric layer;
• patterning the sacrificial polysilicon gate layer and the high-k dielectric layer;
• removing portions of the SG polysilicon layer to form an SG adjacent to the MG;
• depositing an inter-layer dielectric (ILD) to encapsulate the MG, the SG, and a logic field-effect transistor (FET);
• planarizing the ILD;
• removing the sacrificial polysilicon gate layer;
• and
• depositing a metal gate overlying the high-K dielectric layer to form the logic FET field-effect transistor (FET) in the second region.