Memory circuitry having a pair of immediately-adjacent memory arrays having space laterally-there-between that has a conductive interconnect in the space

Memory circuitry comprising:

• a pair of immediately-adjacent memory arrays having space laterally there-between, the memory arrays individually comprising memory cells individually having upper and lower elevationally-extending transistors and a capacitor elevationally there-between;
• the memory arrays comprising individual rows that (a) have an upper access line above and directly electrically coupled to a lower access line, and (b) are directly electrically coupled to one another across the space;
• the lower access line in one of the rows extending across the space from one of the memory arrays to the other of the memory arrays;
• and
• another of the rows comprising a conductive interconnect that includes a horizontally-elongated portion extending across a portion of the space and that is longitudinally-aligned in and with the one row.

Memory circuitry comprising two transistor-one capacitor (2T-1C) memory cells, comprising:

• a pair of immediately-adjacent 2T-1C memory arrays having space laterally there-between, the 2T-1C memory arrays individually comprising 2T-1C memory cells individually comprising upper and lower elevationally-extending transistors having a capacitor elevationally there-between;
• the 2T-1C memory arrays comprising columns of first comparative digit lines at an upper digit line level above and electrically coupled to columns of the upper elevationally-extending transistors, the 2T-1C memory arrays comprising columns of second comparative digit lines at a lower digit line level below and electrically coupled to columns of the lower elevationally-extending transistors;
• the 2T-1C memory arrays sharing first alternating rows and second alternating rows, the second alternating rows individually being between immediately-adjacent of the first alternating rows, individual of the first and second alternating rows having an upper access line in an upper access line level above a lower access line in a lower access line level, the upper access line and the lower access line in the individual first alternating rows and in the individual second alternating rows being directly electrically coupled together, the upper access line and the lower access line in the individual first alternating rows being directly electrically coupled together by a conductor interconnect that includes a horizontally-extending portion within the upper digit line level that is directly above both of the upper access line and the lower access line in that individual first alternating row, the individual first alternating rows in the 2T-1C memory arrays being directly electrically coupled to one another across the space, the individual second alternating rows in the 2T-1C memory arrays not being directly electrically coupled to one another across the space;
• the lower access line in alternating ones of the first alternating rows extending across the space from one of the 2T-1C memory arrays to the other of the 2T-1C memory arrays, the upper access line in alternating others of the first alternating rows not extending across the space from one of the 2T-1C memory arrays to the other of the 2T-1C memory arrays, the alternating other first alternating rows individually being between immediately-adjacent of the alternating ones of the first alternating rows;
• and
• individual of the alternating other first alternating rows in the one and the other 2T-1C memory arrays being directly electrically coupled to one another across the space by a conductive interconnect that includes one horizontally-elongated portion in the space in the upper digit line level and another horizontally-elongated portion in the space in the upper access line level, the another horizontally-elongated portion in the space being directly above the lower access line in an immediately-adjacent one of the alternating ones of the first alternating rows.