Integrated circuits with gate cut features

A method comprising:

• receiving a substrate having a plurality of fins extending from the substrate;
• forming a dielectric layer on a side surface of a first fin of the plurality of fins;
• forming a cut feature alongside the dielectric layer opposite the first fin;
• after the forming of the cut feature, selectively recessing the dielectric layer until the first fin and the cut feature extend above the recessed dielectric layer;
• forming a gate structure on the first fin and the cut feature;
• and
• after the forming of the gate structure, recessing the gate structure to form a first gate structure on the first fin and a second gate structure that is electrically isolated from the first gate structure by the cut feature.

A method comprising:

• receiving a workpiece that includes a substrate and a plurality of fins extending from the substrate;
• forming a first layer on a side surface of each of the plurality of fins such that a first trench and a second trench extend between the plurality of fins, each of the first trench and the second trench being bound by the first layer;
• forming a first cut feature in the first trench and a second cut feature in the second trench;
• after the forming of the first cut feature and the second cut feature, selectively recessing the first layer until the plurality of fins, the first cut feature and the second cut feature extend above the recessed first layer;
• and
• forming a first gate structure on a first fin of the plurality of fins and a second gate structure on a second fin of the plurality of fins such that the first fin is disposed between the first cut feature and the second cut feature and the second cut feature is disposed between the first gate structure and the second gate structure.