Semiconductor device including vertical routing structure and method for manufacturing the same

A semiconductor device, the device comprising:

• a transistor over a substrate, the transistor having a source region and a drain region,
• wherein the source region includes:
• a first via surrounded by a first protective layer in a first interlayer dielectric (ILD) layer on the source region;
• a first metal layer formed on the first via, the first metal layer extending along a first direction;
• a second via surrounded by a second protective layer in a second ILD layer over the first metal layer, the second via overlapping the first via;
• and
• a second metal layer formed on the second via, the second metal layer extending along a second direction different from the first direction, and
• wherein the drain region includes:
• a third via surrounded by a third protective layer in the first ILD layer over the drain region, the third via being at a same height level as the first via;
• a third metal layer formed on the third via;
• a fourth via surrounded by a fourth protective layer in the second ILD layer over the third metal layer, the fourth via overlapping the third via;
• and
• a controlled device disposed on the fourth via, the controlled device being at a same height level as the second metal layer and controlled by the transistor.

A semiconductor device, the device comprising:

• a transistor on a substrate, the transistor having a source region and a drain region 140;
• a member including:
• an interlayer dielectric layer;
• a source-side via in the interlayer dielectric layer formed over the source region and a drain-side via in the interlayer dielectric layer over the drain region;
• and
• a source-side metal layer in contact with the source-side via and a drain-side metal layer in contact with the source-side via, and
• a controlled device on one of an uppermost source-side via and an uppermost drain-side via formed with the member stacked,
• wherein a second interlayer dielectric layer in contact with the drain-side metal layer is made of a second semiconductor material different from a first semiconductor material of a first interlayer dielectric layer in contact with the drain-side via.