Electrostatic discharge handling for lateral transistor devices
AssigneeSemiconductor Components Industries, LLC
InventorHan-Chung Tai
Life of this patent
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Abstract
A semiconductor transistor device includes a source region, a gate region having a p-type gate region and an n-type gate region, and a drain region having a p-type drain region and an n-type drain region. The p-type gate region, the n-type gate region, the p-type drain region, and the n-type drain region are positioned to provide, in response to an electrostatic discharge (ESD) voltage, a drain-to-gate ESD current path to at least partially discharge the ESD voltage.
Claims20
A method of making a semiconductor transistor device, the method comprising:
- forming a source region;
- forming a gate region having a p-type gate region and an n-type gate region;
- forming a drain region having a p-type drain region and an n-type drain region;
- forming a p-well at least partially under the gate region, and electrically shorted to the p-type gate region during an electrostatic discharge (ESD);
- and
- forming an n-well under the source region, the gate region, the p-well, and the drain region, and electrically shorted to the n-type drain region during the ESD.
A method of making a semiconductor transistor device, comprising:
- forming, in a substrate of a first conductivity type, a first well region of a second conductivity type;
- forming a source region of the second conductivity type in the first well region;
- forming a second well region of the first conductivity type in the first well region;
- forming a first gate region having the first conductivity type and in the second well region as part of a gate region;
- forming a second gate region having the second conductivity type in the second well region as part of the gate region;
- forming a first drain region having the second conductivity type in the first well region as part of a drain region;
- and
- forming a second drain region having the first conductivity type in the first well region as part of the drain region,
- wherein at least the second drain region, the first well region, the second well region, and the second gate region form a structure that provides, in response to voltage induced by electrostatic discharge (ESD), a drain-to-gate ESD current path.
A method of making a semiconductor transistor device, the method comprising:
- forming a source region;
- forming a first gate region having a first conductivity type, as part of a gate region;
- forming a second gate region having a second conductivity type, as part of the gate region;
- forming a first drain region having the second conductivity type, as part of a drain region;
- and
- forming a second drain region having the first conductivity type, as part of the drain region,
- forming the drain region at a center portion of the semiconductor transistor device,
- forming the gate region around and surrounding the drain region;
- and
- forming the source region around and surrounding the gate region.
Dependencies are inferred from the claim text.