US 10,872,883 B2 · Memory circuit and method of operating same

Abstract

Memory circuit including a first word line, a first bit line, a second bit line, a first inverter, a second inverter, a P-type pass gate transistor and a pre-charge circuit. The first inverter is coupled to a first storage node. The second inverter is coupled to the first storage node and the first inverter. The P-type pass gate transistor is coupled between the first storage node and the first bit line. The P-type pass gate transistor is coupled to the first word line, the first inverter and the second inverter. The pre-charge circuit is coupled to the first bit line or the second bit line. The pre-charge circuit is configured to charge the first bit line or the second bit line to a pre-charge voltage responsive to a first signal. The pre-charge voltage is between a voltage of a first logical level and a voltage of a second logical level.

Claims20

Dependent claims

A memory circuit comprising:

a first word line;
a first bit line;
a second bit line;
a first inverter coupled to a first storage node;
a second inverter coupled to the first storage node and the first inverter;
a P-type pass gate transistor coupled between the first storage node and the first bit line, and coupled to the first word line, the first inverter and the second inverter;
and
a pre-charge circuit coupled to the first bit line or the second bit line, the pre-charge circuit configured to charge the first bit line or the second bit line to a pre-charge voltage responsive to a first signal, the pre-charge voltage being between a voltage of a first logical level and a voltage of a second logical level.

5 more elements

A memory circuit comprising:

a first word line extending in a first direction;
a first bit line extending in a second direction different from the first direction;
a second bit line extending in the second direction;
a first memory cell between the first bit line and the second bit line, the first memory cell comprising:
a first storage node;
a first P-type pass gate transistor coupled to the first word line, and coupled between the first storage node and the first bit line;
and
a second storage node is not coupled to the second bit line;
a first pre-charge circuit having a first N-type transistor coupled to the first bit line, and configured to charge the first bit line to a pre-charge voltage responsive to a first signal;
and
a second pre-charge circuit having a second N-type transistor coupled to the second bit line, and configured to charge the second bit line to the pre-charge voltage responsive to the first signal, the pre-charge voltage being between a voltage of a first logical level and a voltage of a second logical level.

8 more elements

A method of reading data stored in a first memory cell, the method comprising:

pre-charging, by a set of pre-charge circuits, a first bit line and a second bit line to a pre-charge voltage responsive to a first signal, the pre-charge voltage being between a first voltage of a first logical level and a second voltage of a second logical level, the first bit line being coupled to the first memory cell, the set of pre-charge circuits being coupled to the first bit line and the second bit line, and the data being the first logical level or the second logical level;
turning on a pass gate transistor responsive to a second signal comprises:
coupling the first bit line and a first node of the first memory cell, the second signal being different from the first signal;
and
pulling the pre-charge voltage of the first bit line towards a voltage of the data stored in the first memory cell;
outputting the voltage of the data stored in the first memory cell, the voltage of the data being the first voltage or the second voltage.

3 more elements

Dependencies are inferred from the claim text.

Memory circuit and method of operating same

Life of this patent

Memory circuit and method of operating same

Life of this patent

Abstract

Claims20