US 10,872,880 B2Granted

Land grid array package extension

AssigneeIntel Corporation

InventorsTyler Leuten, Min-Tih Lai

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Abstract

BGA packages with a LGA package extension. First lands on a substrate are populated with solder balls, while only solder paste is dispensed on second lands that are surrounded by the first lands. Differences in solder stand-off may accommodate non-planarity in a package or the insertion of an LGA extension component, such as an IC or one or more discrete devices. Where an LGA extension component is attached to the second lands, solder paste may be further dispensed on third lands located on a package-side of the extension component. A BGA package is then attached to the first lands and third lands. The larger volume BGA solder connections maintaining mechanical reliability, particularly where the solder ball interconnects form a perimeter surrounding the low-volume solder interconnects.

Claims14

Dependent claims

A method of fabricating a microelectronic package assembly, the method comprising:

receiving a substrate;
dispensing solder balls on only some lands of the substrate, the solder balls having a first solder volume;
and
attaching one or more components to a first region of the substrate by reflowing a solder paste of a second solder volume, smaller than the first volume, to a first stand-off height, and attaching the one or more components to a second region of the substrate by reflowing the solder balls to a second stand-off height, greater than the first stand-off height, wherein attaching the one or more components further comprises:
attaching a first of the components to first lands within the first region by reflowing the solder paste;
attaching a second of the components to second lands within the second region by reflowing the solder balls, the second of the components covering the first of the components, and wherein the second stand-off height is at least equal to a thickness of the first of the components summed with the first stand-off height;
and
attaching the second of the components to the lands on a second side of the first of the components by reflowing solder paste between the first and second components.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/387,432Filed 17 Apr 2019 · division
Priority: 28 Dec 2016
Published: US 2019/0244931 A18 Aug 2019
Granted: 22 Dec 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10W 90/00
Package configurations
H10W 70/65
Characterised by their interconnections: shapes or dispositions of interconnections
H10W 70/68
Characterised by their insulating layers or insulating parts: shapes or dispositions thereof
H10W 90/28
Configurations of stacked chips: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape

Family

Application15/392,832Parent of this division · filed 28 Dec 2016
US 2019/0244931 A1Pre-grant publication · published 8 Aug 2019
US 10,304,799 B2Parent of this division
US 2018/0182735 A1Published application
US 10,872,880 B2This patent

From the US filing history. Foreign family members aren’t listed.

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