Chip package structure with dummy bump and method for forming the same

A method for forming a chip package structure, comprising:

• bonding a chip to a first surface of a first substrate;
• forming a bump and a dummy bump over a second surface of the first substrate, wherein the first surface is opposite the second surface, the bump is electrically connected to the chip, and the dummy bump is electrically insulated from the chip;
• cutting through the first substrate and the dummy bump to form a cut substrate and a cut dummy bump, wherein the cut dummy bump is over a corner portion of the cut substrate, and a first sidewall of the cut dummy bump is substantially coplanar with a second sidewall of the cut substrate;
• and
• bonding the cut substrate to a second substrate through the bump and the dummy bump.

A method for forming a chip package structure, comprising:

• bonding a chip to a first surface of a first substrate;
• forming a dummy bump over a second surface of the first substrate, wherein the first surface is opposite the second surface, and the dummy bump is electrically insulated from the chip;
• forming a dummy solder layer over the dummy bump;
• cutting through the first substrate, the dummy bump, and the dummy solder layer to form a cut substrate, a cut dummy bump, and a cut dummy solder layer, wherein the cut dummy bump and the cut dummy solder layer are over a corner portion of the cut substrate, and sidewalls of the cut substrate, the cut dummy bump, and the cut dummy solder layer are substantially coplanar;
• and
• reflowing the cut dummy solder layer to form a dummy solder ball, wherein the dummy solder ball has a curved sidewall in a top view of the dummy solder ball.