Semiconductor package

A semiconductor package comprising:

• a connection member having a first surface and a second surface opposing each other, and including an insulating member and a plurality of redistribution layers on different levels in the insulating member;
• a semiconductor chip disposed on the first surface of the connection member, and including a connection pad connected to the plurality of redistribution layers;
• an encapsulant disposed on the first surface of the connection member, and sealing the semiconductor chip;
• a passivation layer disposed on the second surface of the connection member;
• a plurality of UBM layers including a plurality of UBM pads disposed on the passivation layer, and a plurality of UBM vias passing through the passivation layer, to connect the plurality of UBM pads to the plurality of redistribution layers, respectively;
• and
• a plurality of electrical connection structures respectively disposed on the plurality of UBM pads,
• wherein an interface between the passivation layer and the UBM vias has a first unevenness surface, a surface of an outermost redistribution layer among the plurality of redistribution layers has a second unevenness surface, connected to the first unevenness surface, and the outermost redistribution layer has a surface roughness greater than a surface roughness of the other redistribution layers among the plurality of redistribution layers, and
• wherein the surface roughness of the first unevenness surface and the surface roughness of the second unevenness surface are greater than 1 μm.

A semiconductor package comprising:

• a connection member including a first redistribution layer, a second redistribution layer, an insulating layer disposed between the first and second redistribution layers, and a via layer passing the insulating layer and connecting the first and second redistribution layers to each other;
• a semiconductor chip disposed on the connection member and including a connection pad connected to the second redistribution layer;
• an encapsulant sealing the semiconductor chip;
• a passivation layer disposed on the first redistribution layer and including an opening exposing a portion of the first redistribution layer;
• an underbump metallurgy (UBM) layer connected to the portion of the first redistribution layer through the opening in the passivation layer;
• and
• an electrical connection structure disposed on the UBM layer,
• wherein interfaces between the passivation layer and the UBM layer and between the passivation layer and the first redistribution layer extend continuously from a first contacting portion where the electrical connection structure, the UBM layer, and the passivation layer contact with each other to a second contacting portion where the insulating layer of the connection member, the first redistribution layer, and the passivation layer contact with each other, and have a surface roughness greater than a surface roughness of the second redistribution layer, and
• wherein the surface roughness of the interfaces between the passivation layer and the UMB layer and between the passivation layer and the first redistribution layer is greater than 1 μm.