Semiconductor package

A semiconductor package comprising:

• a connection structure including an insulating layer, a wiring layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the wiring layer;
• a frame disposed on the connection structure and having one or more through-holes;
• a semiconductor chip and passive components disposed in the one or more through-holes of the frame on the connection structure;
• a first encapsulant covering at least portions of the passive components and the frame and forming a through-hole;
• a frame wiring layer disposed on the frame;
• a location identifying mark disposed around the semiconductor chip on the frame and spaced apart from the frame wiring layer;
• and
• a second encapsulant covering at least a portion of the semiconductor chip,
• wherein at least a portion of the location identifying mark is not covered by the first encapsulant,
• wherein the second encapsulant covers side surfaces and an upper surface of the semiconductor chip, and the first encapsulant, and
• wherein the second encapsulant covers an exposed portion of the location identifying mark which is not covered by the first encapsulant.

A semiconductor package comprising:

• a frame having an upper surface, a lower surface opposing the upper surface, and a through-hole extending from the upper surface to the lower surface;
• a semiconductor chip disposed in the through-hole;
• and
• a plurality of identifying marks symmetrically disposed relative to the semiconductor chip on the upper surface of the frame,
• wherein a metal layer is disposed on inner walls of the frame forming the through-hole.