Wafer level package utilizing molded interposer

A semiconductor package, comprising:

• a molded interposer, comprising:
• a layer of first molding compound having a first side and a second side opposite to the first side;
• a first redistribution layer (RDL) structure disposed on the first side;
• a second redistribution layer (RDL) structure disposed on the second side;
• a plurality of metal vias embedded in the layer of first molding compound electrically connecting the first RDL structure with the second RDL structure;
• and
• passive devices, each passive device comprising a first side facing the first RDL structure and an opposite second side facing the second RDL structure, each passive device completely embedded in and completely surrounded by the layer of first molding compound, wherein each passive device is electrically connected to the first RDL structure through a plurality of connecting elements extending directly, vertically between the first RDL structure and the first side of each respective passive device, wherein the plurality of connecting elements are embedded in the layer of first molding compound and surrounded by the layer of first molding compound;
• semiconductor dice mounted on the first RDL structure and electrically connected thereto on a side of the first RDL structure opposite the passive device, each semiconductor die of the semiconductor dice being electrically connected to, and having a footprint covering, a corresponding one of the passive devices by a direct, vertical connection utilizing the plurality of connecting elements to form a face-to-face connection between each semiconductor die and the corresponding one of the passive devices;
• and
• a plurality of solder balls mounted on the second RDL structure.