Semiconductor package

A semiconductor package comprising:

• a connection member including an insulating member and a plurality of redistribution layers disposed on different levels of the insulating member;
• a semiconductor chip disposed on the connection member and having connection pads electrically connected to the plurality of redistribution layers;
• an encapsulant disposed on a first surface of the connection member and encapsulating the semiconductor chip;
• and
• a wiring structure having a bottom end connected to the plurality of redistribution layers and a top end exposing from an upper surface of the encapsulant,
• wherein at least one redistribution layer of the plurality of redistribution layers includes a dummy electrode pattern having a plurality of holes, and each of the plurality of holes has a concave polygonal shape,
• wherein a redistribution layer adjacent to the at least one redistribution layer includes a wiring pattern having a region overlapped with the plurality of holes, and the wiring pattern of the redistribution layer has a line width narrower than a maximum width of the plurality of holes,
• wherein a width of the region of the wiring pattern overlapped with the plurality of holes is approximately equal to a width of other regions or is smaller than the width of the other regions by less than 10%.

A semiconductor package comprising:

• a connection member having a first surface and a second surface opposing each other and including an insulating member and a plurality of redistribution layers disposed on different levels of the insulating member;
• a supporting member disposed on the first surface of the connection member and having a cavity accommodating the semiconductor chip;
• a semiconductor chip disposed on the connection member in the cavity and having connection pads electrically connected to the plurality of redistribution layers;
• an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip,
• a passivation layer disposed on the second surface of the connection member;
• a plurality of UBM layer disposed on the passivation layer, and electrically connected to the plurality of redistribution layers through an insulating layer;
• and
• a plurality of electrical connection structures disposed on the plurality of UBM layers, respectively,
• wherein the plurality of redistribution layers include a first redistribution layer disposed on a first level and connected to the connection pads of the semiconductor chip, and a second redistribution layer disposed on a second level adjacent to the first level and connected to the first redistribution layer,
• wherein the first redistribution layer includes a first dummy electrode pattern having a plurality of first holes, each of the plurality of first holes having a concave polygonal shape, and the second redistribution layer includes a wiring pattern having a region overlapped with the plurality of first holes and having a line width narrower than a maximum width of the plurality of first holes,
• wherein the concave polygonal shape has a central region and a plurality of protruding regions protruding from the central region, a width of each the plurality of protruding regions being less than twice the line width of the wiring pattern of the second redistribution layer.