Solid top terminal for discrete power devices

A method comprising:

• forming a transistor on a die of a wafer, wherein the transistor comprises a first electrode and a second electrode;
• forming a first conductor on the die, wherein the first conductor is a conductive layer electrically coupled to the first electrode;
• cutting the die from the wafer after the first conductor is formed thereon;
• plating a second conductor including a first lead with a conductive material;
• sintering the plated second conductor directly with the first conductor after the first die is cut from the wafer;
• forming a fourth conductor on the die, wherein the fourth conductor is a conductive layer electrically coupled to the second electrode;
• plating a fifth conductor including a second lead with the conductive material;
• and
• sintering the plated fourth conductor directly with the fourth conductor after the first die is cut from the wafer,
• wherein the transistor comprises an insulated-gate bipolar transistor (IGBT), and
• wherein the first electrode comprises a collector of the IGBT.

An apparatus comprising:

• a substrate comprising a first conductive material;
• a die mounted on the substrate, the die comprising a transistor, the transistor comprising a first electrode and a second electrode;
• and
• a first conductor electrically coupled to the first electrode and fused directly to a plated second conductor including a first lead;
• a third conductor electrically coupled to the second electrode and fused directly to a plated fourth conductor including a second lead;
• wherein the first conductor and the second conductor comprise conductive layers, and
• wherein the transistor comprises an insulated-gate bipolar transistor (IGBT), and wherein the first electrode comprises a collector of the IGBT.