Method for manufacturing semiconductor device

A method comprising:

• forming a first fin of a first core circuit and a second fin of a second core circuit over a substrate;
• forming a first gate electrode across the first fin and a second gate electrode across the second fin;
• forming a first source/drain adjoining the first fin and a second source/drain adjoining the second fin;
• forming a first contact over the first source/drain and a second contact over the second source/drain;
• and
• forming a first via over the first contact and a second via over the second contact, wherein an area of a top surface of the second via is greater than an area of a top surface of the first via, and a width of the second via measured along a lengthwise direction of the second fin is greater than a width of the first contact measured along a lengthwise direction of the first fin.

A method comprising:

• modelling in a layout first and second fins extending along a direction;
• modelling in the layout a first gate electrode superimposed over the first fin and a second gate electrode superimposed over the second fin;
• modelling in the layout a first source/drain contact superimposed over the first fin and having a first width measured along the direction;
• modelling in the layout a second source/drain contact superimposed over the second fin and having a second width measured along the direction, wherein the second width of the second source/drain contact is greater than the first width of the first source/drain contact;
• and
• forming physical first and second fins, physical first and second gate electrodes, and physical first and second source/drain contacts in an integrated circuit using the first and second fins, the first and second gate electrodes, and the first and second source/drain contacts as patterns.