Package structure for heat dissipation
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen
Life of this patent
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Abstract
A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material.
Claims20
A device comprising:
- a first die, the first die comprising a first set of vias traversing completely through the first die and a first dielectric material surrounding the first set of vias;
- a second die, the second die comprising a second set of vias traversing completely through the second die and a second dielectric material surrounding the second set of vias, the first set of vias being aligned with and bonded to the second set of vias, wherein the first dielectric material is bonded to the second dielectric material, and wherein the first set of vias are directly bonded to the second set of vias without solder;
- a first molding compound material disposed on sidewalls of the first die;
- and
- a second molding compound material disposed on sidewalls of the second die.
A die stack structure, comprising:
- a first device, comprising a semiconductor substrate, the semiconductor substrate having a metal feature disposed at a surface thereof, the semiconductor substrate comprising active elements;
- a second device comprising a substrate and a plurality of conductive vias traversing through an entire thickness of the substrate, wherein the plurality of conductive vias are disposed in the substrate aligned to an adjacent plurality of conductive vias of the first device at a first surface of the second device, wherein a first conductive via of the plurality of conductive vias is bonded to the metal feature of the first device;
- a third device comprising a metal feature disposed at a surface of the third device, wherein the metal feature of the third device is bonded to the first conductive via;
- a first molding compound material disposed on sidewalls of the second device;
- and
- a second molding compound material disposed on sidewalls of the third device, an outer sidewall of the second molding compound material aligned to an outer sidewall of the semiconductor substrate of the first device.
A package structure, comprising:
- a substrate comprising a logic area and a memory area, a first surface of the substrate having connectors formed thereon, and a second surface of the substrate being opposite the first surface, the logic area comprising a logic device formed in the substrate;
- a memory die stack attached to the second surface of the substrate in the memory area;
- a first heat dissipating structure attached to the second surface of the substrate in the logic area;
- and
- a thermal interface material disposed over and laterally surrounding the memory die stack and first heat dissipating structure.
Dependencies are inferred from the claim text.