Integrated circuit structures

A device structure, comprising:

• a body, comprising a monocrystalline semiconductor material, adjacent to an isolation dielectric;
• a gate stack adjacent to a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric;
• a source and a drain coupled to the body on opposite sides of the gate stack;
• a front-side interconnect metallization layer coupled to at least one of the source, drain, or gate electrode;
• and
• a back-side device layer over a back-side surface of the body, opposite the front-side interconnect metallization layer, wherein the back-side device layer comprises a second semiconductor material having a different composition than that of the body;
• and
• a back-side device terminal electrically coupled to the back-side device layer, wherein:
• the structure comprises a field effect transistor (FET) stacked over a thin film transistor (TFT);
• the second semiconductor material is polycrystalline or amorphous;
• a second gate stack is coupled to the second semiconductor material;
• and
• the back-side device terminal further comprises a source or drain of the TFT, which is coupled to the second semiconductor material.

An integrated circuit (IC) structure, comprising:

• a transistor body adjacent to a field isolation dielectric, the transistor body comprising a monocrystalline semiconductor material;
• a gate stack adjacent to a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric;
• a source and a drain coupled to the transistor body on opposite sides of the gate stack;
• a front-side interconnect metallization layer over a first side of the transistor body and the field isolation dielectric, the front-side interconnect metallization layer coupled to a first one of the source, drain, or gate electrode;
• and
• a back-side interconnect metallization layer over a second side of the body and the field isolation dielectric, the back-side interconnect metallization layer coupled to a second one of the source, drain, or gate electrode, and wherein the front-side interconnect metallization layer comprises an alloy having more Cu than any metal alloy of the back-side interconnect metallization layer, or the back-side interconnect metallization layer comprises an alloy having more Cu than any metal alloy of the front-side interconnect metallization layer.