Semiconductor device and method of fabricating the same

A method of fabricating a semiconductor device, the method comprising:

• forming a lower wiring;
• forming an etch stop layer on the lower wiring;
• forming an interlayer insulating film covering the lower wiring and the etch stop layer;
• forming a via in the interlayer insulating film, the via exposing an upper surface of the etch stop layer;
• forming a first filler in the via;
• etching the first filler to form a first filler pattern;
• forming a second filler on the first filler pattern within the via;
• etching the second filler to form a second filler pattern;
• forming a third filler on the second filler pattern within the via;
• etching the third filler to form a third filler pattern;
• etching the interlayer insulating film to form a trench;
• etching the first, second and third filler patterns, during the forming of the trench, to form a residual filler pattern;
• removing the residual filler pattern and the etch stop layer;
• and
• forming a wiring structure within the via and the trench, the wiring structurre being electrically connected to the lower wiring,
• wherein the via comprises a lower portion and an upper portion disposed on the lower portion, and
• wherein the trench comprises the upper portion of the via.

A method fabricating a semiconductor device, the method comprising:

• forming a lower wiring;
• forming an etch stop layer on the lower wiring;
• forming an interlayer insulating film coveting the lower wiring and the etch stop layer;
• forming a via in the interlayer insulating film, the via exposing an upper surface of the etch stop layer;
• forming a first filler in the via;
• etching the first filler to form a first filler pattern;
• forming a second filler on the first filler pattern within the via;
• etching the second filler to form a second filler pattern;
• etching the interlayer insulating film to form a trench;
• etching the first and second filler patterns, during the forming of the trench, to form a residual filler pattern;
• removing the residual filler pattern and the etch stop layer;
• and
• forming a wiring structure within the via and the trench, the wiring structure being electrically connected to the lower wiring,
• wherein the via comprises a lower portion and an upper portion disposed on the lower portion,
• wherein the trench comprises the upper portion of the via,
• wherein the via comprises a first portion filled with the first filler and a second portion not filled with the first filler, and a first damaged region is formed in the interlayer insulating film along sidewalls of the second portion when the first filler is etched, and
• wherein the via comprises a third portion filled with the second filler and a fourth portion not filled with the second filler, the third portion is a part of the first portion, and a second damaged region is formed in the interlayer insulating film along sidewalls of the fourth portion when the second filler is etched.