Methods of reducing pattern roughness in semiconductor fabrication

A method, comprising:

• patterning a metallic layer disposed over a semiconductor substrate, the patterned metallic layer including a line feature and a roughness feature disposed on an edge of the line feature, wherein the line feature is defined by a first width and the roughness feature is defined by a second width;
• immersing the patterned metallic layer in an electrolyte solution;
• and
• applying a voltage to the patterned metallic layer, thereby reducing the second width relative to the first width.

A method, comprising:

• depositing a dielectric layer over a semiconductor layer;
• depositing a metallic layer over the dielectric layer;
• forming a first pattern in the metallic layer, wherein the first pattern includes a first roughness feature;
• treating the first pattern with an ionic solution, resulting in a second pattern that includes a second roughness feature, wherein the second roughness feature is narrower than the first roughness feature;
• and
• subsequently patterning the dielectric layer.