Shift register unit, gate drive circuit and driving method thereof

A gate drive circuit, comprising:

• a plurality of cascaded shift register units, each of the cascaded shift register units comprising an input sub-circuit, an output control sub-circuit, an output sub-circuit, and a noise reduction sub-circuit comprising a first noise reduction sub-circuit and a second noise reduction sub-circuit, wherein:
• the input sub-circuit is coupled to a first node and a first voltage terminal, and is configured to output a first voltage signal supplied by the first voltage terminal to the first node in response to an input control signal;
• the output control sub-circuit is coupled to the first node, a second node, and a clock signal terminal, and is configured to output an output control signal to the second node in response to the first voltage signal and a clock signal supplied by the clock signal terminal;
• the output sub-circuit is coupled to the second node, a DC voltage terminal, and an output terminal, and is configured to output a DC voltage signal supplied by the DC voltage terminal to the output terminal under control of the output control signal;
• the first noise reduction sub-circuit is coupled to a second voltage terminal and the output control sub-circuit, and is configured to perform noise reduction on the output control sub-circuit in response to a second voltage signal supplied by the second voltage terminal;
• the second noise reduction sub-circuit comprises a noise reduction control sub-circuit, a second node noise reduction sub-circuit, and an output terminal noise reduction sub-circuit;
• the noise reduction control sub-circuit is coupled to a third voltage terminal, the first node, the second node noise reduction sub-circuit, and the output terminal noise reduction sub-circuit, and is configured to output a noise reduction control signal to the second node noise reduction sub-circuit and the output terminal noise reduction sub-circuit under control of a voltage signal at the first node and a third voltage signal supplied by the third voltage terminal;
• the second node noise reduction sub-circuit is coupled to the second node and is configured to perform noise reduction on the second node under control of the noise reduction control signal;
• and
• the output terminal noise reduction sub-circuit is coupled to the output terminal and is configured to perform noise reduction on the output terminal under control of the noise reduction control signal.

A driving method for a gate drive circuit, comprising:

• providing a plurality of cascaded shift register units, each of the cascaded shift register units comprising an input sub-circuit, an output control sub-circuit, an output sub-circuit, and a noise reduction sub-circuit comprising a first noise reduction sub-circuit and a second noise reduction sub-circuit, wherein:
• the input sub-circuit is coupled to a first node and a first voltage terminal, and is configured to output a first voltage signal supplied by the first voltage terminal to the first node in response to an input control signal;
• the output control sub-circuit is coupled to the first node, a second node, and a clock signal terminal, and is configured to output an output control signal to the second node in response to the first voltage signal and a clock signal supplied by the clock signal terminal;
• the output sub-circuit is coupled to the second node, a DC voltage terminal, and an output terminal, and is configured to output a DC voltage signal supplied by the DC voltage terminal to the output terminal under control of the output control signal;
• the first noise reduction sub-circuit is coupled to a second voltage terminal and the output control sub-circuit;
• and
• the second noise reduction sub-circuit comprises a noise reduction control sub-circuit, a second node noise reduction sub-circuit, and an output terminal noise reduction sub-circuit, the noise reduction control sub-circuit being coupled to a third voltage terminal, the first node, the second node noise reduction sub-circuit, and the output terminal noise reduction sub-circuit, the second node noise reduction sub-circuit being coupled to the second node, and the output terminal noise reduction sub-circuit being coupled to the output terminal;
• before an input phase and at a noise reduction phase, performing, by the first noise reduction sub-circuit, noise reduction on the output control sub-circuit in response to a second voltage signal supplied by the second voltage terminal;
• at the input phase, outputting, by the input sub-circuit, the first voltage signal supplied by the first voltage terminal to the first node in response to the input control signal;
• at an output phase, outputting, by the output control sub-circuit, the output control signal to the second node in response to the first voltage signal and the clock signal supplied by the clock signal terminal;
• and
• outputting the DC voltage signal supplied by the DC voltage terminal to the output terminal under control of the output control signal, wherein the noise reduction phase further comprises:
• outputting, by the noise reduction control sub-circuit, a noise reduction control signal to the second node noise reduction sub-circuit and the output terminal noise reduction sub-circuit under control of a voltage signal of the first node and a third voltage signal supplied by the third voltage terminal;
• and
• performing, by the second node noise reduction sub-circuit, noise reduction on the second node and performing, by the output terminal noise reduction sub-circuit, noise reduction on the output terminal, under control of the noise reduction control signal.