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US 10,872,669 B2Granted
Semiconductor device and a manufacturing method of the semiconductor device
AssigneeSK hynix Inc.
InventorEun Young Park
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a bit line, a source line, and a memory string coupled between the bit line and the source line. The memory string includes at least one drain select transistor, a plurality of memory cells, at least one source select transistor, and a dummy transistor coupled between the bit line and the drain select transistor or between the source line and the source select transistor.
Claims18
A semiconductor device comprising:
- a bit line;
- a source line;
- a plurality of memory strings coupled between the bit line and the source line, wherein each of the plurality of memory strings comprises:
- at least one drain select transistor;
- a plurality of memory cells;
- at least one source select transistor;
- and
- a dummy transistor coupled between the bit line and the drain select transistor or between the source line and the source select transistor;
- a peripheral circuit configured to perform an erase operation, a program operation or a read operation on the memory strings by applying bias to dummy lines coupled to dummy transistors of the memory strings;
- and
- a control logic configured to control the peripheral circuit, wherein the control logic is configured to control the peripheral circuit such that the bias varies according to threshold voltages of the dummy transistors.
8 more elements
A semiconductor device comprising:
- a bit line;
- a source line;
- a plurality of memory strings coupled between the bit line and the source line, wherein each of the plurality of memory strings comprises:
- at least one drain select transistor;
- a plurality of memory cells;
- at least one source select transistor;
- and
- a dummy transistor coupled between the bit line and the at least one drain select transistor or between the source line and the source select transistor;
- a peripheral circuit configured to perform an erase operation, a program operation or a read operation on the memory strings by applying bias to dummy lines coupled to dummy transistors of the memory strings;
- and
- a control logic configured to control the peripheral circuit, wherein the control logic is configured to control the peripheral circuit such that the bias varies according to junction overlaps of channel structures included in the memory strings.
8 more elements
A semiconductor device comprising:
- stacked structures each including word lines, at least one select line stacked over the word lines, and at least one dummy line stacked over the at least one select line;
- openings passing through the stacked structures;
- channel layers formed in the openings;
- pads formed in the openings, wherein the pads are coupled to the channel layers, respectively;
- a peripheral circuit configured to apply bias to dummy lines during an erase operation, a program operation, or a read operation;
- and
- a control logic configured to control the peripheral circuit such that the bias varies depending on heights of the pads.
4 more elements
Dependencies are inferred from the claim text.