Source line management for memory cells with floating gates
AssigneeMicron Technology, Inc.
InventorRichard E. Fackenthal
Life of this patent
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Abstract
Methods, systems, and devices for source line configurations for a memory device are described. In some cases, a memory cell of the memory device may include a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor coupled with the floating gate of the first transistor. The memory cell may be coupled with a word line, a digit line, and a source line. During a write operation, the source line may be clamped to the digit line using one or more memory cells in the memory device. During a read operation, the source line may be grounded using one or more memory cells in the memory device.
Claims9
An apparatus, comprising:
- an array of memory cells, each memory cell of the array of memory cells comprising a first transistor that includes a control gate and a floating gate and a second transistor connected with the floating gate of the first transistor, wherein each memory cell is configured to store a logic state using the first transistor and second transistor;
- a plurality of word lines, each word line connected with control gates of the first transistors and gates of the second transistors of memory cells of a row of the array;
- a plurality of digit lines, each digit line connected with a first node of the first transistors and a second node of the second transistors of memory cells of a column of the array;
- and
- a plurality of source lines, each source line corresponding to one digit line of the plurality of digit lines and connected with a second node of the first transistor of a respective memory cell that is connected with the one digit line, each source line configured to be biased based on an operation being performed using the one digit line.
Dependencies are inferred from the claim text.